asicsforthemasses / LunaPnR
LunaPnR is a place and router for integrated circuits
☆44Updated this week
Related projects ⓘ
Alternatives and complementary repositories for LunaPnR
- A padring generator for ASICs☆22Updated last year
- ☆36Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- ☆33Updated 2 years ago
- SAR ADC on tiny tapeout☆35Updated 2 weeks ago
- submission repository for efabless mpw6 shuttle☆30Updated 10 months ago
- This repository is for (pre-)release versions of the Revolution EDA.☆35Updated 2 weeks ago
- An open source PDK using TIGFET 10nm devices.☆43Updated last year
- An automatic clock gating utility☆43Updated 4 months ago
- Generate symbols from HDL components/modules☆20Updated last year
- Virtual development board for HDL design☆39Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 5 months ago
- USB virtual model in C++ for Verilog☆28Updated last month
- ☆26Updated 3 years ago
- ☆22Updated last year
- Bitstream relocation and manipulation tool.☆40Updated last year
- ☆30Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆41Updated 2 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆42Updated this week
- ☆39Updated last year
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆16Updated last year
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- Wishbone interconnect utilities☆37Updated 6 months ago
- ☆29Updated 2 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆73Updated 2 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- RISC-V Nox core☆61Updated 3 months ago
- Characterizer☆21Updated 3 months ago
- Flip flop setup, hold & metastability explorer tool☆31Updated 2 years ago