asicsforthemasses / LunaPnR

Related projects ⓘ

Alternatives and complementary repositories for LunaPnR

• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• b224hisl / rioschip
  ☆32Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆17Updated 4 months ago
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆35Updated this week
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆20Updated last year
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆23Updated this week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆40Updated 3 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆39Updated last year
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated 9 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆31Updated 2 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆36Updated 5 months ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆31Updated this week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆63Updated 2 months ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆26Updated 3 weeks ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆28Updated 3 weeks ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆67Updated 6 months ago
• RTimothyEdwards / capiche
  Parasitic capacitance analysis of foundry metal stackups
  ☆10Updated last month
• CESNET / sphinx-vhdl
  ☆21Updated 3 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆27Updated 3 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆41Updated 2 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆46Updated this week
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆22Updated 7 months ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆18Updated last year
• FPGA-Research-Manchester / byteman
  Bitstream relocation and manipulation tool.
  ☆39Updated last year
• pulp-platform / cheshire-ihp130-o
  ☆25Updated last month
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆35Updated last year