asicsforthemasses / LunaPnRLinks
LunaPnR is a place and router for integrated circuits
☆47Updated 3 months ago
Alternatives and similar repositories for LunaPnR
Users that are interested in LunaPnR are comparing it to the libraries listed below
Sorting:
- ☆38Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- ☆32Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆38Updated last week
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆48Updated 3 years ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆17Updated 3 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆108Updated 2 months ago
- An automatic clock gating utility☆51Updated 6 months ago
- USB virtual model in C++ for Verilog☆32Updated last year
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆63Updated 2 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆79Updated 3 weeks ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆91Updated this week
- SpiceBind – spice inside HDL simulator☆56Updated 4 months ago
- ☆38Updated 2 years ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆29Updated this week
- Fabric generator and CAD tools graphical frontend☆17Updated 3 months ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 11 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated last week