asicsforthemasses / LunaPnRLinks
LunaPnR is a place and router for integrated circuits
☆47Updated 2 months ago
Alternatives and similar repositories for LunaPnR
Users that are interested in LunaPnR are comparing it to the libraries listed below
Sorting:
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- ☆38Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated 3 weeks ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 3 years ago
- USB virtual model in C++ for Verilog☆31Updated 11 months ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆48Updated 3 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- ☆39Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated 3 weeks ago
- An automatic clock gating utility☆50Updated 5 months ago
- SAR ADC on tiny tapeout☆42Updated 8 months ago
- ☆33Updated 2 years ago
- Library of reusable VHDL components☆28Updated last year
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 4 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- SpiceBind – spice inside HDL simulator☆55Updated 3 months ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆57Updated 3 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆71Updated last month
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆29Updated last month
- Yosys plugin for logic locking and supply-chain security☆22Updated 5 months ago
- ☆17Updated 10 months ago
- ☆70Updated last year