asicsforthemasses / LunaPnR
LunaPnR is a place and router for integrated circuits
☆46Updated 3 months ago
Alternatives and similar repositories for LunaPnR:
Users that are interested in LunaPnR are comparing it to the libraries listed below
- A padring generator for ASICs☆25Updated last year
- ☆36Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- An automatic clock gating utility☆43Updated 7 months ago
- FPGA250 aboard the eFabless Caravel☆28Updated 4 years ago
- Virtual development board for HDL design☆40Updated last year
- ☆33Updated 2 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆42Updated 2 years ago
- SAR ADC on tiny tapeout☆39Updated 3 weeks ago
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- Characterizer☆21Updated 5 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆47Updated 2 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated 2 weeks ago
- ☆31Updated last month
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 2 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆54Updated this week
- Small SERV-based SoC primarily for OpenMPW tapeout☆38Updated 2 months ago
- USB virtual model in C++ for Verilog☆29Updated 4 months ago
- ☆32Updated 4 months ago
- ☆26Updated this week
- ☆22Updated last year
- ☆33Updated 3 months ago
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- ☆39Updated 2 years ago
- PicoRV☆44Updated 5 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- Library of reusable VHDL components☆27Updated 11 months ago