asicsforthemasses / LunaPnRLinks
LunaPnR is a place and router for integrated circuits
☆47Updated 6 months ago
Alternatives and similar repositories for LunaPnR
Users that are interested in LunaPnR are comparing it to the libraries listed below
Sorting:
- A padring generator for ASICs☆25Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 3 years ago
- ☆38Updated 3 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- Virtual development board for HDL design☆42Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆31Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- ☆33Updated 3 years ago
- ☆38Updated 3 years ago
- SAR ADC on tiny tapeout☆45Updated last year
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆87Updated 3 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated last week
- Specification of the Wishbone SoC Interconnect Architecture☆49Updated 3 years ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆13Updated this week
- Convert an image to a GDS format for inclusion in a zerotoasic project☆18Updated 3 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆54Updated last month
- Fabric generator and CAD tools graphical frontend☆17Updated 5 months ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- An automatic clock gating utility☆52Updated 9 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- PicoRV☆43Updated 5 years ago
- An open source PDK using TIGFET 10nm devices.☆55Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆56Updated last week
- an inverter drawn in magic with makefile to simulate☆27Updated 3 years ago