efabless / sky130_sram_macros_oldLinks
☆37Updated 3 years ago
Alternatives and similar repositories for sky130_sram_macros_old
Users that are interested in sky130_sram_macros_old are comparing it to the libraries listed below
Sorting:
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 5 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- An automatic clock gating utility☆49Updated 2 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Xilinx Unisim Library in Verilog☆78Updated 4 years ago
- A configurable SRAM generator☆53Updated this week
- A padring generator for ASICs☆25Updated 2 years ago
- ☆33Updated 2 years ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆49Updated 5 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- ☆32Updated 6 months ago
- Open source process design kit for 28nm open process☆59Updated last year
- Python interface to FPGA interchange format☆41Updated 2 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆115Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆44Updated last month
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆89Updated 6 years ago
- Characterizer☆28Updated last month
- Prefix tree adder space exploration library☆57Updated 7 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆71Updated 10 months ago
- Demo SoC for SiliconCompiler.☆59Updated last month
- BAG framework☆41Updated 11 months ago
- ☆55Updated last year
- ☆48Updated 5 months ago
- A simple DDR3 memory controller☆56Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 7 months ago