Alternatives and similar repositories for sky130_sram_macros_old:

Users that are interested in sky130_sram_macros_old are comparing it to the libraries listed below

• AUCOHL / Lighter
  An automatic clock gating utility
  ☆46Updated 8 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• pulp-platform / svase
  ☆31Updated 3 months ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆27Updated 2 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆87Updated this week
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆48Updated 2 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 4 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• snishizawa / libretto
  Characterizer
  ☆22Updated 7 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated 3 weeks ago
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆13Updated 8 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 11 months ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 7 months ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆47Updated 3 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆38Updated 11 months ago
• shalan / Awesome-Sky130-IPs
  ☆10Updated last year
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• mattvenn / openlane_summary
  ☆21Updated last year
• efabless / caravel_user_project_analog
  ☆45Updated 2 months ago
• vsdip / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆15Updated 4 years ago
• efabless / caravel-lite
  ☆16Updated 5 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 9 months ago
• siliconcompiler / lambdapdk
  Library of open source Process Design Kits (PDKs)
  ☆37Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆52Updated 11 months ago