efabless / sky130_sram_macros_oldLinks
☆38Updated 3 years ago
Alternatives and similar repositories for sky130_sram_macros_old
Users that are interested in sky130_sram_macros_old are comparing it to the libraries listed below
Sorting:
- An automatic clock gating utility☆50Updated 6 months ago
- A configurable SRAM generator☆56Updated 2 months ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- ☆32Updated 9 months ago
- Prefix tree adder space exploration library☆56Updated 11 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆37Updated last week
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 10 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 9 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 3 months ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- RISC-V Nox core☆68Updated 3 months ago
- ☆43Updated 3 years ago
- ☆56Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆115Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 3 months ago
- Mutation Cover with Yosys (MCY)☆87Updated last week
- Open source process design kit for 28nm open process☆65Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago