waviousllc / wav-lpddr-hw
Wavious DDR (WDDR) Physical interface (PHY) Hardware
☆103Updated 3 years ago
Alternatives and similar repositories for wav-lpddr-hw:
Users that are interested in wav-lpddr-hw are comparing it to the libraries listed below
- A simple DDR3 memory controller☆54Updated 2 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆133Updated this week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆64Updated this week
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Control and status register code generator toolchain☆130Updated this week
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- ☆92Updated last year
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆155Updated 3 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 8 months ago
- UART models for cocotb☆28Updated 2 years ago
- Control and Status Register map generator for HDL projects☆116Updated this week
- Open-source high performance AXI4-based HyperRAM memory controller☆74Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆59Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- General Purpose AXI Direct Memory Access☆49Updated 11 months ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆60Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- Python Tool for UVM Testbench Generation☆52Updated 11 months ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆65Updated 6 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆38Updated 3 months ago
- Platform Level Interrupt Controller☆40Updated 11 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆59Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆69Updated 2 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- Announcements related to Verilator☆39Updated 4 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago