waviousllc / wav-lpddr-hwLinks
Wavious DDR (WDDR) Physical interface (PHY) Hardware
☆122Updated 4 years ago
Alternatives and similar repositories for wav-lpddr-hw
Users that are interested in wav-lpddr-hw are comparing it to the libraries listed below
Sorting:
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆148Updated 3 weeks ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆164Updated 2 months ago
- ☆113Updated 2 months ago
- A simple DDR3 memory controller☆61Updated 3 years ago
- Mathematical Functions in Verilog☆96Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆186Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 6 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Python Tool for UVM Testbench Generation☆55Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- Ethernet interface modules for Cocotb☆74Updated 4 months ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 8 months ago
- Platform Level Interrupt Controller☆44Updated last year
- Repository gathering basic modules for CDC purpose☆58Updated 6 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆137Updated this week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- AXI4 and AXI4-Lite interface definitions☆101Updated 5 years ago
- Network on Chip Implementation written in SytemVerilog☆197Updated 3 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆73Updated 4 months ago
- PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities☆130Updated last week
- ideas and eda software for vlsi design☆51Updated this week
- A complete open-source design-for-testing (DFT) Solution☆178Updated 5 months ago
- An example Python-based MDV testbench for apbi2c core☆30Updated last year