waviousllc / wav-lpddr-hwLinks
Wavious DDR (WDDR) Physical interface (PHY) Hardware
☆121Updated 4 years ago
Alternatives and similar repositories for wav-lpddr-hw
Users that are interested in wav-lpddr-hw are comparing it to the libraries listed below
Sorting:
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated 2 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆144Updated last week
- A simple DDR3 memory controller☆61Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆80Updated last week
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- ☆113Updated 2 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- Python Tool for UVM Testbench Generation☆55Updated last year
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆79Updated last year
- General Purpose AXI Direct Memory Access☆62Updated last year
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities☆128Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 6 months ago
- Announcements related to Verilator☆43Updated 2 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Introductory course into static timing analysis (STA).☆99Updated 6 months ago
- Ethernet interface modules for Cocotb☆73Updated 4 months ago
- Network on Chip Implementation written in SytemVerilog☆196Updated 3 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆71Updated 3 months ago
- Platform Level Interrupt Controller☆43Updated last year
- Repository gathering basic modules for CDC purpose☆57Updated 6 years ago
- A complete open-source design-for-testing (DFT) Solution☆176Updated 4 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆77Updated 5 months ago
- Yet Another RISC-V Implementation☆99Updated last year
- AXI4 and AXI4-Lite interface definitions☆102Updated 5 years ago
- ☆58Updated 9 months ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago