waviousllc / wav-lpddr-hw
Wavious DDR (WDDR) Physical interface (PHY) Hardware
☆101Updated 3 years ago
Alternatives and similar repositories for wav-lpddr-hw:
Users that are interested in wav-lpddr-hw are comparing it to the libraries listed below
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆134Updated 2 weeks ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆35Updated last month
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Pre-packaged testbenching tools and reusable bus interfaces for cocotb☆62Updated 5 months ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆52Updated 4 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- ☆88Updated last year
- SystemVerilog modules and classes commonly used for verification☆46Updated 2 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆65Updated 2 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆58Updated 4 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Control and status register code generator toolchain☆115Updated this week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 6 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- Python Tool for UVM Testbench Generation☆50Updated 9 months ago
- SDRAM controller with AXI4 interface☆88Updated 5 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆57Updated this week
- Platform Level Interrupt Controller☆36Updated 10 months ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- UART models for cocotb☆26Updated 2 years ago
- Announcements related to Verilator☆39Updated 4 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated this week
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 6 months ago