Alternatives and similar repositories for wav-lpddr-hw

Users that are interested in wav-lpddr-hw are comparing it to the libraries listed below

• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆140Updated this week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆156Updated 2 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆118Updated last year
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆62Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆69Updated 8 months ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆176Updated 9 months ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆42Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆44Updated 7 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated last month
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆50Updated 3 weeks ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆126Updated last month
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆59Updated 2 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆94Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆119Updated 2 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆75Updated last month
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆58Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆113Updated 2 weeks ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆74Updated 2 years ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆124Updated 3 months ago
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆66Updated last week
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆58Updated last year
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆157Updated 6 months ago