StanfordVLSI / dragonphy2Links
Open Source PHY v2
☆31Updated last year
Alternatives and similar repositories for dragonphy2
Users that are interested in dragonphy2 are comparing it to the libraries listed below
Sorting:
- An open source PDK using TIGFET 10nm devices.☆53Updated 3 years ago
- ☆44Updated 5 years ago
- Open source process design kit for 28nm open process☆69Updated last year
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- A configurable SRAM generator☆56Updated 4 months ago
- Automatic generation of real number models from analog circuits☆47Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆33Updated 4 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆24Updated 4 years ago
- ☆20Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆143Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆26Updated 6 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated last year
- ☆43Updated 3 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆50Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- APB UVC ported to Verilator☆11Updated 2 years ago
- Common SystemVerilog RTL modules for RgGen☆15Updated last week
- An open source, parameterized SystemVerilog digital hardware IP library☆30Updated last year
- ideas and eda software for vlsi design☆51Updated this week
- LAYout with Gridded Objects☆31Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Python library for parsing module definitions and instantiations from SystemVerilog files☆25Updated 4 years ago