StanfordVLSI / dragonphy2
Open Source PHY v2
☆26Updated 10 months ago
Alternatives and similar repositories for dragonphy2:
Users that are interested in dragonphy2 are comparing it to the libraries listed below
- tools regarding on analog modeling, validation, and generation☆22Updated last year
- An open source PDK using TIGFET 10nm devices.☆47Updated 2 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆22Updated 3 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Open source process design kit for 28nm open process☆50Updated 10 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- ☆40Updated 3 years ago
- ☆31Updated 2 months ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- ☆16Updated 2 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 3 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 8 months ago
- Characterizer☆21Updated 6 months ago
- ☆41Updated 5 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- Running Python code in SystemVerilog☆67Updated 7 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- A configurable SRAM generator☆44Updated 2 months ago
- APB UVC ported to Verilator☆11Updated last year
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆44Updated 4 years ago
- ☆31Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- ☆26Updated last year
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆25Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆63Updated last month
- Python Tool for UVM Testbench Generation☆50Updated 9 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- Python library for operations with VCD and other digital wave files☆47Updated 9 months ago