StanfordVLSI / dragonphy2Links
Open Source PHY v2
☆30Updated last year
Alternatives and similar repositories for dragonphy2
Users that are interested in dragonphy2 are comparing it to the libraries listed below
Sorting:
- tools regarding on analog modeling, validation, and generation☆22Updated 2 years ago
- ☆44Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 7 months ago
- Open source process design kit for 28nm open process☆61Updated last year
- Automatic generation of real number models from analog circuits☆43Updated last year
- An open source PDK using TIGFET 10nm devices.☆50Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated last week
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆47Updated 4 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- A configurable SRAM generator☆54Updated 3 weeks ago
- ☆67Updated 2 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- Library of open source Process Design Kits (PDKs)☆51Updated last week
- Running Python code in SystemVerilog☆70Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- ☆42Updated 3 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆32Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- ☆33Updated 2 years ago
- APB UVC ported to Verilator☆11Updated last year
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated last month
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 4 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆35Updated 8 months ago