StanfordVLSI / dragonphy2
Open Source PHY v2
☆25Updated 9 months ago
Alternatives and similar repositories for dragonphy2:
Users that are interested in dragonphy2 are comparing it to the libraries listed below
- An open source PDK using TIGFET 10nm devices.☆47Updated 2 years ago
- tools regarding on analog modeling, validation, and generation☆21Updated last year
- A configurable SRAM generator☆42Updated last month
- APB UVC ported to Verilator☆11Updated last year
- Python library for parsing module definitions and instantiations from SystemVerilog files☆22Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆31Updated 3 months ago
- ☆20Updated 3 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆35Updated 2 years ago
- Automatic generation of real number models from analog circuits☆37Updated 10 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Open source process design kit for 28nm open process☆48Updated 9 months ago
- ☆40Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- ☆40Updated 5 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- ☆13Updated 7 months ago
- ☆36Updated 2 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆37Updated 4 years ago
- ☆31Updated last month
- SRAM☆21Updated 4 years ago
- ideas and eda software for vlsi design☆49Updated last week
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 3 months ago
- Characterizer☆21Updated 5 months ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated last month
- ☆16Updated 2 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Running Python code in SystemVerilog☆67Updated 6 months ago