tgingold / OpenTDC

Related projects ⓘ

Alternatives and complementary repositories for OpenTDC

• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆26Updated 3 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last month
• yrrapt / caravel_amsat_txrx_ic
  ☆29Updated 3 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• andrewattwood / fuserisc
  Dual RISC-V DISC with integrated eFPGA
  ☆15Updated 3 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 7 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆22Updated 4 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆53Updated last year
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• efabless / caravel-lite
  ☆15Updated this week
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆36Updated 9 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆40Updated last month
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆31Updated this week
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆19Updated 2 years ago
• b224hisl / rioschip
  ☆32Updated last year
• milovanovic / caravel_spectrometer
  ☆11Updated 3 years ago
• FPGA-Research-Manchester / byteman
  Bitstream relocation and manipulation tool.
  ☆39Updated last year
• Victoromoniyi / gr-litex
  LiteX Accelerator Block for GNU Radio
  ☆24Updated 2 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆60Updated 2 weeks ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• paulscherrerinstitute / xvcSupport
  ☆17Updated 4 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆16Updated this week
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆42Updated this week
• tongchen126 / fpga_pcie_ethernet
  ☆14Updated 2 years ago
• controlpaths / blog
  Projects published on controlpaths.com and hackster.io
  ☆39Updated 2 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆23Updated 5 years ago
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆51Updated last year
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆29Updated last year