Alternatives and similar repositories for caravel_amsat_txrx_ic:

Users that are interested in caravel_amsat_txrx_ic are comparing it to the libraries listed below

• tclarke / sky130radio
  components and examples for creating radio ICs using the open skywater 130nm PDK
  ☆18Updated 4 years ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 3 years ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆72Updated 3 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• rnunes2311 / SAR_ADC_12bit
  12 bit SAR ADC IP in Skywater 130 nm PDK
  ☆15Updated 9 months ago
• yrrapt / analogue_design_example
  An example of analogue design using open source IC design tools
  ☆29Updated 3 years ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• rnunes2311 / tt07-12bit_SAR_ADC
  12 bit SAR ADC for TinyTapeout 7
  ☆12Updated 9 months ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆39Updated last month
• westonb / sky130-analog
  Analog and power building blocks for sky130 pdk
  ☆20Updated 4 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆30Updated 4 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆41Updated 2 months ago
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆16Updated last year
• christoph-weiser / mpw7
  Efabless mpw7 submission
  ☆13Updated 10 months ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆20Updated 3 weeks ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆24Updated 2 weeks ago
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆36Updated 3 years ago
• diadatp / sky130_rf_tools
  Guides and templates for using open source RF design tools with the SkyWater SKY130 process.
  ☆19Updated 4 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆22Updated 9 years ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆21Updated 6 years ago
• milovanovic / caravel_spectrometer
  ☆12Updated 4 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• EMIL-YORKU / SensSeq
  A mixed-signal system on chip for nanopore-based DNA sequencing
  ☆34Updated 2 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆21Updated last year
• mabrains / PLL_design
  PLL Designs on Skywater 130nm MPW
  ☆20Updated last year