Alternatives and similar repositories for usb3_pipe

Users that are interested in usb3_pipe are comparing it to the libraries listed below

• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆236Updated 3 years ago
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆265Updated 6 years ago
• Xilinx / XilinxVirtualCable
  Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or S…
  ☆264Updated 2 months ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆97Updated 5 years ago
• derekmulcahy / xvcpi
  Xilinx Virtual Cable Server for Raspberry Pi
  ☆124Updated 3 years ago
• tmbinc / xvcd
  Xilinx Virtual Cable Daemon
  ☆124Updated 10 months ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆186Updated last year
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆319Updated last year
• enjoy-digital / liteeth
  Small footprint and configurable Ethernet core
  ☆272Updated this week
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆346Updated 2 months ago
• davidthings / tinyfpga_bx_usbserial
  USB Serial on the TinyFPGA BX
  ☆139Updated 4 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆84Updated 4 years ago
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆100Updated 6 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆130Updated 3 years ago
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆176Updated last year
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆184Updated this week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆252Updated last year
• damdoy / ice40_ultraplus_examples
  Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
  ☆290Updated last year
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated 2 years ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆145Updated 3 years ago
• j-marjanovic / jtag-quartus-ft232h
  ☆54Updated 3 years ago
• RHSResearchLLC / NiteFury-and-LiteFury
  Public repository for Litefury & Nitefury
  ☆310Updated last year
• RHSResearchLLC / PicoEVB
  Public repository for PicoEVB (Xilinx Artix XC7A50T based)
  ☆263Updated last month
• Parretto / DisplayPort
  DisplayPort IP-core
  ☆83Updated 3 weeks ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆85Updated 2 years ago
• ultraembedded / FPGAmp
  720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
  ☆291Updated 5 years ago
• ZipCPU / dblclockfft
  A configurable C++ generator of pipelined Verilog FFT cores
  ☆251Updated last year
• TiferKing / ypcb_00338_1p1_hack
  YPCB-00338-1P1 Hack
  ☆75Updated last year
• jakubcabal / spi-fpga
  SPI master and SPI slave for FPGA written in VHDL
  ☆180Updated 4 years ago
• fjullien / migen_litex_tutorials
  ☆117Updated 2 years ago