USB3 PIPE interface for Xilinx 7-Series
☆252Jan 2, 2026Updated 2 months ago
Alternatives and similar repositories for usb3_pipe
Users that are interested in usb3_pipe are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Test of the USB3 IP Core from Daisho on a Xilinx device☆102Oct 3, 2019Updated 6 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102May 16, 2023Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Feb 20, 2026Updated last month
- FPGA USB stack written in LiteX☆133Jun 5, 2022Updated 3 years ago
- ice40 USB Analyzer☆57Aug 8, 2020Updated 5 years ago
- Gowin USB3.0 Device Controller IP☆15Aug 20, 2024Updated last year
- A full-speed device-side USB peripheral core written in Verilog.☆237Oct 30, 2022Updated 3 years ago
- Amaranth HDL framework for monitoring, hacking, and developing USB devices☆1,097Aug 22, 2025Updated 7 months ago
- USB Full-Speed core written in migen/LiteX☆17Sep 2, 2019Updated 6 years ago
- SuperSpeed USB 3.0 FPGA platform☆264Apr 9, 2015Updated 10 years ago
- A configurable USB 2.0 device core☆32Jun 12, 2020Updated 5 years ago
- PCIe analyzer experiments☆67May 21, 2020Updated 5 years ago
- ECP5 breakout board in a feather physical format☆524Nov 6, 2024Updated last year
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆97Jun 6, 2020Updated 5 years ago
- PCB for ULX3S FPGA R&D board☆425Apr 27, 2025Updated 10 months ago
- Small footprint and configurable PCIe core☆670Updated this week
- A Verilog implementation of DisplayPort protocol for FPGAs☆268Mar 15, 2019Updated 7 years ago
- Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)☆259Aug 21, 2023Updated 2 years ago
- Various HDL (Verilog) IP Cores☆879Jul 1, 2021Updated 4 years ago
- Bluetooth PHY based on one-bit input and output☆241Apr 11, 2021Updated 4 years ago
- An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!☆220May 21, 2022Updated 3 years ago
- USB -> AXI Debug Bridge☆43Jun 5, 2021Updated 4 years ago
- Documenting Lattice's 28nm FPGA parts☆149Feb 26, 2026Updated 3 weeks ago
- Ultimate ECP5 development board☆116Jul 4, 2019Updated 6 years ago
- Small footprint and configurable JESD204B core☆53Feb 11, 2026Updated last month
- Basic USB 1.1 Host Controller for small FPGAs☆98Jun 6, 2020Updated 5 years ago
- Siglent SDS1x0xX-E FPGA bitstreams☆46Dec 24, 2024Updated last year
- ☆31Apr 1, 2017Updated 8 years ago
- Build your hardware, easily!☆3,787Updated this week
- Drop In USB CDC ACM core for iCE40 FPGA☆34Sep 5, 2021Updated 4 years ago
- USB Serial on the TinyFPGA BX☆142Jun 20, 2021Updated 4 years ago
- An open source USB bootloader for FPGAs☆397Sep 15, 2023Updated 2 years ago
- Debug and parallel trace hardware for CORTEX-M (FPGA + support code)☆170Feb 6, 2026Updated last month
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Implementation of the PCIe physical layer☆61Jul 11, 2025Updated 8 months ago
- Linux on LiteX-VexRiscv☆694Mar 6, 2026Updated 2 weeks ago
- Universal utility for programming FPGA☆1,576Mar 18, 2026Updated last week
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Aug 7, 2023Updated 2 years ago
- micropython ESP32 programmer/flasher for ECP5 JTAG☆74Sep 14, 2025Updated 6 months ago