siliconcompiler / zerosocLinks
Demo SoC for SiliconCompiler.
☆62Updated last week
Alternatives and similar repositories for zerosoc
Users that are interested in zerosoc are comparing it to the libraries listed below
Sorting:
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆92Updated 6 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Updated 2 years ago
- Bitstream relocation and manipulation tool.☆51Updated 3 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- Naive Educational RISC V processor☆94Updated 3 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- FuseSoC standard core library☆151Updated 2 months ago
- ☆33Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- Open Source AES☆31Updated 4 months ago
- RISC-V Nox core☆71Updated 6 months ago
- ☆38Updated 3 years ago
- Python interface to FPGA interchange format☆41Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆90Updated 3 weeks ago
- ☆60Updated 4 years ago
- An automatic clock gating utility☆52Updated 9 months ago
- FPGA250 aboard the eFabless Caravel☆32Updated 5 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated this week
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆107Updated 4 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- PicoRV☆43Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆49Updated last month
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆70Updated last month