siliconcompiler / zerosoc
Demo SoC for SiliconCompiler.
☆57Updated 2 weeks ago
Alternatives and similar repositories for zerosoc:
Users that are interested in zerosoc are comparing it to the libraries listed below
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- SoftCPU/SoC engine-V☆54Updated this week
- FuseSoC standard core library☆128Updated last month
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆94Updated 3 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆79Updated last week
- ☆59Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆39Updated last year
- Yet Another RISC-V Implementation☆90Updated 6 months ago
- ☆36Updated 2 years ago
- Wishbone interconnect utilities☆39Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆82Updated 10 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆40Updated 3 months ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆80Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 10 months ago
- Mutation Cover with Yosys (MCY)☆80Updated last week
- Simple runtime for Pulp platforms☆42Updated last week
- Bitstream relocation and manipulation tool.☆43Updated 2 years ago
- Spen's Official OpenOCD Mirror☆48Updated last week
- A pipelined RISC-V processor☆52Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆77Updated last week
- ☆33Updated 2 years ago
- Open source ISS and logic RISC-V 32 bit project☆43Updated 3 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆75Updated 3 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆45Updated 5 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆87Updated 5 years ago
- Naive Educational RISC V processor☆79Updated 5 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆87Updated 5 years ago