siliconcompiler / zerosocLinks
Demo SoC for SiliconCompiler.
☆60Updated this week
Alternatives and similar repositories for zerosoc
Users that are interested in zerosoc are comparing it to the libraries listed below
Sorting:
- Xilinx Unisim Library in Verilog☆84Updated 5 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Mutation Cover with Yosys (MCY)☆85Updated 2 weeks ago
- Naive Educational RISC V processor☆87Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆117Updated last year
- FuseSoC standard core library☆146Updated 2 months ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆105Updated last week
- Yet Another RISC-V Implementation☆96Updated 11 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- ☆33Updated 2 years ago
- ☆38Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- ☆59Updated 3 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- Open Source AES☆31Updated last year
- PicoRV☆44Updated 5 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- ☆79Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆46Updated 2 months ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- ☆107Updated last week
- A pipelined RISC-V processor☆57Updated last year
- RISC-V Nox core☆68Updated last month
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- An Open Source configuration of the Arty platform☆131Updated last year