d-m-bailey / cvc

Related projects ⓘ

Alternatives and complementary repositories for cvc

• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 2 years ago
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆22Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• bluecheetah / bag
  BAG framework
  ☆41Updated 3 months ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated 9 months ago
• westonb / sky130-analog
  Analog and power building blocks for sky130 pdk
  ☆20Updated 3 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆42Updated 6 months ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆17Updated 6 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆43Updated last year
• RTimothyEdwards / capiche
  Parasitic capacitance analysis of foundry metal stackups
  ☆10Updated last month
• mabrains / PLL_design
  PLL Designs on Skywater 130nm MPW
  ☆20Updated 11 months ago
• vsdip / avsddac_3v3_sky130_v1
  ☆11Updated 2 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆21Updated 4 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• pradeepsk13 / vsdsram_sky130_1.8V
  Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node
  ☆13Updated 3 years ago
• Deepak42074 / vsdsram_sky130
  Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns
  ☆11Updated 3 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
  7 track standard cells for GF180MCU provided by GlobalFoundries.
  ☆22Updated last year
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆19Updated 4 months ago
• ACMmodel / MOSFET_model
  A simple MOSFET model with only 5-DC-parameters for circuit simulation
  ☆38Updated 4 months ago
• snishizawa / libretto
  Characterizer
  ☆20Updated 2 months ago
• ieee-ceda-datc / datc-rdf-calibrations
  ☆16Updated last week
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆37Updated 5 years ago
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 3 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆37Updated 7 months ago
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆12Updated 8 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆20Updated 5 years ago
• mabrains / Analog_blocks
  Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.
  ☆26Updated 2 years ago