CVC: Circuit Validity Checker. Check for errors in CDL netlist.
☆33Dec 25, 2025Updated 2 months ago
Alternatives and similar repositories for cvc
Users that are interested in cvc are comparing it to the libraries listed below
Sorting:
- This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.☆22Feb 15, 2024Updated 2 years ago
- gaw3-20200922 fork with patches to improve remote commands sent from xschem to display waveforms☆17Mar 28, 2025Updated 11 months ago
- ☆19Oct 28, 2024Updated last year
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Feb 13, 2020Updated 6 years ago
- Hdl21 Schematics☆16Jan 24, 2024Updated 2 years ago
- IRSIM switch-level simulator for digital circuits☆36Nov 13, 2025Updated 3 months ago
- This package provides a gnucap based qucsator implementation.☆15Feb 3, 2026Updated last month
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- ☆38Jul 11, 2022Updated 3 years ago
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆51Mar 13, 2025Updated 11 months ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Sep 24, 2021Updated 4 years ago
- Parasitic Extraction for KLayout☆39Feb 20, 2026Updated last week
- Netgen complete LVS tool for comparing SPICE or verilog netlists☆129Feb 3, 2026Updated last month
- KLayout technology files for Skywater SKY130☆44Jul 19, 2023Updated 2 years ago
- Qrouter detail router for digital ASIC designs☆57Nov 13, 2025Updated 3 months ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆77Mar 28, 2025Updated 11 months ago
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 10 months ago
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆50Sep 8, 2025Updated 5 months ago
- ☆59Jul 11, 2025Updated 7 months ago
- Verilog hardware abstraction library☆46Feb 23, 2026Updated last week
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆20Sep 19, 2023Updated 2 years ago
- Circuit Automatic Characterization Engine☆52Feb 7, 2025Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Sep 8, 2020Updated 5 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆40Jun 10, 2021Updated 4 years ago
- A complete open-source design-for-testing (DFT) Solution☆180Aug 30, 2025Updated 6 months ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆395Updated this week
- Convert an image to a GDS format for inclusion in a zerotoasic project☆18Jun 16, 2022Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 2 weeks ago
- GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk☆16Jun 3, 2021Updated 4 years ago
- Parasitic capacitance analysis of foundry metal stackups☆17Jan 12, 2026Updated last month
- autorouter forked from https://www-soc.lip6.fr/git/coriolis.git☆15May 21, 2018Updated 7 years ago
- Zero to ASIC group submission for MPW2☆13Mar 26, 2025Updated 11 months ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆27Dec 1, 2022Updated 3 years ago
- A library and command-line tool for querying a Verilog netlist.☆29Jun 13, 2022Updated 3 years ago
- Builds, flow and designs for the alpha release☆54Dec 18, 2019Updated 6 years ago
- ☆33Jul 28, 2020Updated 5 years ago
- Source-Opened RISCV for Crypto☆18Jan 18, 2022Updated 4 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆70Nov 26, 2025Updated 3 months ago
- SRAM macros created for the GF180MCU provided by GlobalFoundries.☆19Apr 10, 2023Updated 2 years ago