Verilog RTL Design
☆47Sep 4, 2021Updated 4 years ago
Alternatives and similar repositories for SerDes
Users that are interested in SerDes are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆25Feb 22, 2024Updated 2 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆277Mar 26, 2022Updated 4 years ago
- RTL code of some arbitration algorithm☆16Aug 25, 2019Updated 6 years ago
- Verilog for ASIC Design☆32Sep 13, 2021Updated 4 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆18Jun 24, 2021Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆85Oct 2, 2019Updated 6 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆15Mar 26, 2024Updated 2 years ago
- To design test bench of the APB protocol☆19Dec 30, 2020Updated 5 years ago
- A simple PDM microphone interface on FPGA☆14Jan 16, 2022Updated 4 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆18Jan 28, 2022Updated 4 years ago
- ☆18Feb 26, 2024Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Source code for "Combined Neural Network and Adaptive DSP Training for Long-Haul Optical Communications" (JLT 2021)☆41Feb 3, 2026Updated 2 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- UVM Testbench for synchronus fifo☆19Aug 28, 2020Updated 5 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- ☆14Jul 28, 2022Updated 3 years ago
- 🪐Optical Communications python library (GPU supported for FIBER simulation)☆21Feb 7, 2026Updated 2 months ago
- An 8b10b decoder and encoder in logic in VHDL☆26Apr 12, 2021Updated 5 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆19Oct 18, 2023Updated 2 years ago
- A survey of manufacturer-provided DRAM operating parameters and timings as specified by DRAM chip datasheets from between 1970 and 2021. …☆11May 4, 2022Updated 3 years ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆19Oct 23, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- 12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm☆25May 13, 2023Updated 2 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆35Jan 2, 2024Updated 2 years ago
- Explanation of FPGA code for 8 PDM microphones in Matrix Creator☆15Nov 9, 2020Updated 5 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆38Feb 6, 2019Updated 7 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Nov 18, 2012Updated 13 years ago
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆61Jan 10, 2024Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆79Jan 2, 2021Updated 5 years ago
- ☆20Aug 4, 2022Updated 3 years ago
- ☆18Apr 5, 2015Updated 11 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)☆16Dec 24, 2020Updated 5 years ago
- NTU Computer Architecture 2021 - CPU with Single issue, L1-cache☆11Jan 24, 2022Updated 4 years ago
- Demo for Melexis MLX90640 sensor using mikromedia 7 for STM32F7☆19Dec 9, 2021Updated 4 years ago
- Repository for VSD-IAT Workshop: Physical Verification using SKY130☆10Aug 15, 2021Updated 4 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆14Jul 22, 2020Updated 5 years ago
- All design files, source code, and documentation for Project OAK, a digital watch inspired by mechanical complications.☆26Dec 14, 2025Updated 4 months ago
- LiteX based FPGA gateware for Thunderscope.☆30Mar 23, 2026Updated 3 weeks ago