ishfaqahmed29 / SerDes
Verilog RTL Design
☆32Updated 3 years ago
Alternatives and similar repositories for SerDes:
Users that are interested in SerDes are comparing it to the libraries listed below
- UART -> AXI Bridge☆60Updated 3 years ago
- ☆25Updated 3 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- A simple DDR3 memory controller☆54Updated 2 years ago
- Verilog Content Addressable Memory Module☆104Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 10 months ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 4 months ago
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆53Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆15Updated last year
- ☆23Updated last year
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- Xilinx AXI VIP example of use☆34Updated 3 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- Complete tutorial code.☆17Updated 10 months ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- A 2D convolution hardware implementation written in Verilog☆44Updated 4 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 8 years ago
- ☆40Updated 3 years ago
- AXI Interconnect☆47Updated 3 years ago