ishfaqahmed29 / SerDes
Verilog RTL Design
☆24Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for SerDes
- 128KB AXI cache (32-bit in, 256-bit out)☆44Updated 3 years ago
- UART -> AXI Bridge☆57Updated 3 years ago
- ☆23Updated 3 years ago
- The memory model was leveraged from micron.☆19Updated 6 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- To design test bench of the APB protocol☆15Updated 3 years ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆36Updated 3 years ago
- An open source, parameterized SystemVerilog digital hardware IP library☆23Updated 5 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology☆17Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆43Updated 11 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆36Updated 11 months ago
- A simple DDR3 memory controller☆51Updated last year
- IEEE P1735 decryptor for VHDL☆26Updated 9 years ago
- ☆10Updated 2 years ago
- A 2D convolution hardware implementation written in Verilog☆42Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- A compact, configurable RISC-V core☆11Updated last week
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- ☆10Updated 4 months ago
- ☆14Updated last month
- Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer☆26Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆13Updated 4 months ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- A 32 point radix-2 FFT module written in Verilog☆20Updated 4 years ago
- ☆10Updated 9 months ago