ishfaqahmed29 / SerDesLinks
Verilog RTL Design
☆46Updated 4 years ago
Alternatives and similar repositories for SerDes
Users that are interested in SerDes are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆61Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- UART -> AXI Bridge☆67Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆76Updated 6 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- Implementation of the PCIe physical layer☆59Updated 4 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆52Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆56Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆69Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆73Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆37Updated 3 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆88Updated last year
- Structured UVM Course☆52Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆95Updated last year
- ☆52Updated 4 years ago
- A 2D convolution hardware implementation written in Verilog☆51Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- Asynchronous fifo in verilog☆37Updated 9 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- The memory model was leveraged from micron.☆24Updated 7 years ago
- ☆43Updated 3 years ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago