mattvenn / multi_project_toolsLinks
tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
☆36Updated 2 years ago
Alternatives and similar repositories for multi_project_tools
Users that are interested in multi_project_tools are comparing it to the libraries listed below
Sorting:
- ☆43Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- An open source PDK using TIGFET 10nm devices.☆54Updated 2 years ago
- ☆38Updated 3 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated last year
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆48Updated 8 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆40Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Characterizer☆30Updated 2 weeks ago
- ☆33Updated 10 months ago
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆137Updated last week
- FPGA250 aboard the eFabless Caravel☆32Updated 4 years ago
- ☆12Updated 3 years ago
- An automatic clock gating utility☆51Updated 7 months ago
- ☆14Updated 2 years ago
- SystemVerilog Linter based on pyslang☆31Updated 6 months ago
- A padring generator for ASICs☆25Updated 2 years ago
- ☆26Updated 3 months ago
- LunaPnR is a place and router for integrated circuits☆47Updated 4 months ago
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆61Updated 3 months ago
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆76Updated 5 years ago
- SpiceBind – spice inside HDL simulator☆56Updated 5 months ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 10 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 5 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- PLL Designs on Skywater 130nm MPW☆22Updated 2 years ago