FPGA-Research / FABulousLinks
Fabric generator and CAD tools.
☆196Updated this week
Alternatives and similar repositories for FABulous
Users that are interested in FABulous are comparing it to the libraries listed below
Sorting:
- Standard Cell Library based Memory Compiler using FF/Latch cells☆156Updated 2 months ago
- SystemVerilog synthesis tool☆209Updated 6 months ago
- FuseSoC standard core library☆147Updated 3 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆137Updated 3 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆137Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆140Updated this week
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated last year
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆231Updated last week
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆116Updated 4 years ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆347Updated 6 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆312Updated 6 months ago
- ASIC implementation flow infrastructure☆108Updated last week
- SystemVerilog frontend for Yosys☆157Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆84Updated last year
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆45Updated 7 months ago
- ☆83Updated 2 years ago
- WAL enables programmable waveform analysis.☆155Updated 3 months ago
- Open-source FPGA research and prototyping framework.☆208Updated last year
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆119Updated 2 months ago
- A complete open-source design-for-testing (DFT) Solution☆164Updated 2 weeks ago
- RISC-V System on Chip Template☆159Updated 3 weeks ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆141Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆109Updated 4 years ago
- https://caravel-user-project.readthedocs.io☆217Updated 6 months ago
- Control and status register code generator toolchain☆143Updated 2 weeks ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆292Updated 4 months ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆188Updated 4 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆175Updated 9 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆288Updated 2 months ago