FPGA-Research / FABulousLinks
Fabric generator and CAD tools.
☆206Updated this week
Alternatives and similar repositories for FABulous
Users that are interested in FABulous are comparing it to the libraries listed below
Sorting:
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated this week
- SystemVerilog synthesis tool☆217Updated 8 months ago
- ASIC implementation flow infrastructure☆173Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆151Updated this week
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆117Updated 4 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- SystemVerilog frontend for Yosys☆168Updated this week
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆193Updated this week
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆319Updated 8 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆237Updated 2 months ago
- Open-source FPGA research and prototyping framework.☆209Updated last year
- Fully Open Source FASOC generators built on top of open-source EDA tools☆296Updated 3 weeks ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆221Updated last year
- A complete open-source design-for-testing (DFT) Solution☆168Updated 2 months ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆254Updated 3 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last month
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆301Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 11 months ago
- ☆84Updated 3 years ago
- FuseSoC standard core library☆148Updated 5 months ago
- Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.☆363Updated 8 months ago
- ☆119Updated 2 years ago
- WAL enables programmable waveform analysis.☆160Updated this week
- Control and status register code generator toolchain☆152Updated this week
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆66Updated last month
- VeeR EL2 Core☆303Updated this week