Alternatives and similar repositories for FABulous

Users that are interested in FABulous are comparing it to the libraries listed below

• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆158Updated 3 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆211Updated 6 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆165Updated last week
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆119Updated 2 years ago
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆116Updated 4 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆233Updated last month
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆140Updated last month
• librelane / librelane
  ASIC implementation flow infrastructure
  ☆125Updated this week
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆208Updated last year
• sscs-ose / sscs-ose-code-a-chip.github.io
  IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)
  ☆188Updated last week
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆313Updated 7 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆112Updated 4 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆121Updated 2 months ago
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆218Updated 7 months ago
• google / sky90fd-pdk
  ☆116Updated 2 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆164Updated last month
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆292Updated 3 months ago
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆142Updated 2 years ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆147Updated last week
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆217Updated 11 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆84Updated last year
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆349Updated 7 months ago
• efabless / chipignite-resources
  ☆83Updated 2 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆176Updated 10 months ago
• ncsu-eda / FreePDK3
  ☆174Updated 4 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆140Updated this week
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆61Updated last week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆157Updated 4 months ago