Alternatives and similar repositories for FABulous:

Users that are interested in FABulous are comparing it to the libraries listed below

• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆138Updated 7 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆176Updated this week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆157Updated 2 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆205Updated 2 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆143Updated 2 months ago
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆102Updated 3 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆130Updated 3 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆155Updated 3 weeks ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆130Updated last month
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆120Updated 3 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆141Updated 2 months ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆164Updated 2 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆264Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆112Updated 3 weeks ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆306Updated this week
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆124Updated 3 weeks ago
• RTimothyEdwards / open_pdks
  PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…
  ☆304Updated this week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆299Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆377Updated last month
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆116Updated 3 months ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆170Updated last month
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆155Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆257Updated this week
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆155Updated 4 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆241Updated this week
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆252Updated 2 months ago
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆134Updated 2 years ago