richard259 / serdespyLinks
Python library for SerDes modelling
☆73Updated last year
Alternatives and similar repositories for serdespy
Users that are interested in serdespy are comparing it to the libraries listed below
Sorting:
- Gm Id Kit with GUI to Work with Matlab Data file similar to Prof. Boris Murmann's gm/ID Starter Kit☆47Updated 5 years ago
- repository for a bandgap voltage reference in SKY130 technology☆39Updated 2 years ago
- Python script for generating lookup tables for the gm/ID design methodology and much more ...☆96Updated 4 months ago
- LAYout with Gridded Objects☆29Updated 5 years ago
- HSPICE and MATLAB simulation files of a tracking SAR ADC☆25Updated last year
- Verilog RTL Design☆43Updated 3 years ago
- ADC Performance Survey (ISSCC & VLSI Circuit Symposium)☆210Updated last week
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Updated 6 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆72Updated 2 years ago
- ☆164Updated 3 years ago
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 8 years ago
- LAYout with Gridded Objects v2☆62Updated 2 months ago
- This repo contains introduction of gm/id method and its application to some OTA design examples.☆18Updated last year
- Read Spectre PSF files☆66Updated 3 weeks ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆187Updated 3 months ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆95Updated last year
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆56Updated 2 weeks ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆158Updated 3 weeks ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆68Updated 5 months ago
- ☆24Updated 3 years ago
- A python3 gm/ID starter kit☆52Updated 2 weeks ago
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆33Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆75Updated 4 years ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆163Updated 3 weeks ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆172Updated 9 months ago
- Sandbox for experimenting with Ngspice and open PDKs in Google Colab☆24Updated last year
- Verilog-A simulation models☆78Updated 3 weeks ago
- Automatic generation of real number models from analog circuits☆43Updated last year
- Successive Approximation Register (SAR) ADC Digital Calibration (in Matlab)☆65Updated 7 years ago