lakshmi-sathi / avsdpll_1v8Links
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
☆118Updated 4 years ago
Alternatives and similar repositories for avsdpll_1v8
Users that are interested in avsdpll_1v8 are comparing it to the libraries listed below
Sorting:
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- Fabric generator and CAD tools.☆214Updated this week
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆144Updated 2 years ago
- FuseSoC standard core library☆150Updated 2 weeks ago
- ☆85Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆46Updated 5 years ago
- Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
- ☆44Updated 10 months ago
- ☆88Updated 2 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- An automatic clock gating utility☆51Updated 8 months ago
- SystemVerilog frontend for Yosys☆184Updated this week
- ☆43Updated 3 years ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆67Updated 3 weeks ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 5 months ago
- ☆38Updated 3 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆164Updated 2 years ago
- SpinalHDL Hardware Math Library☆93Updated last year
- A simple DDR3 memory controller☆61Updated 2 years ago
- An open-source HDL register code generator fast enough to run in real time.☆78Updated last week
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Verilog wishbone components☆124Updated last year
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- An example of analogue design using open source IC design tools☆29Updated 4 years ago
- This repository is for (pre-)release versions of the Revolution EDA.☆57Updated 2 weeks ago
- This repo is a fork of the master OpenLANE repo for us with projects submitted on Efabless Open MPW or chipIgnite shuttles:: OpenLANE is …☆160Updated last year