lakshmi-sathi / avsdpll_1v8Links
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
☆113Updated 3 years ago
Alternatives and similar repositories for avsdpll_1v8
Users that are interested in avsdpll_1v8 are comparing it to the libraries listed below
Sorting:
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- ☆78Updated 2 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- FuseSoC standard core library☆143Updated 3 weeks ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆63Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆114Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated last year
- ☆111Updated 2 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- SystemVerilog frontend for Yosys☆128Updated this week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 4 months ago
- An example of analogue design using open source IC design tools☆29Updated 3 years ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆65Updated 2 months ago
- ☆47Updated 4 months ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆139Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Prefix tree adder space exploration library☆57Updated 7 months ago
- Python script to transform a VCD file to wavedrom format☆77Updated 2 years ago
- Playing around with Formal Verification of Verilog and VHDL☆58Updated 4 years ago
- ☆79Updated last year
- ☆134Updated 6 months ago
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆63Updated last month
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆171Updated last week
- ☆41Updated 3 years ago
- Verilog digital signal processing components☆143Updated 2 years ago
- Fabric generator and CAD tools.☆187Updated last week
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆48Updated last week
- ☆40Updated 4 months ago
- SpinalHDL Hardware Math Library☆87Updated 11 months ago