lakshmi-sathi / avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
☆110Updated 3 years ago
Alternatives and similar repositories for avsdpll_1v8:
Users that are interested in avsdpll_1v8 are comparing it to the libraries listed below
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆134Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- Playing around with Formal Verification of Verilog and VHDL☆55Updated 4 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 2 months ago
- ☆79Updated 2 years ago
- JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.☆59Updated this week
- XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.☆61Updated last week
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆47Updated this week
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆65Updated 4 years ago
- FuseSoC standard core library☆130Updated 2 months ago
- An example of analogue design using open source IC design tools☆29Updated 3 years ago
- ☆45Updated last month
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- SystemVerilog frontend for Yosys☆81Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Prefix tree adder space exploration library☆57Updated 4 months ago
- Learning to do things with the Skywater 130nm process☆77Updated 4 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆151Updated 3 years ago
- This repository is for (pre-)release versions of the Revolution EDA.☆42Updated last week
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- ☆40Updated 3 years ago
- Control and Status Register map generator for HDL projects☆114Updated last month
- ☆39Updated 2 years ago
- Home of the open-source EDA course.☆35Updated 2 weeks ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆159Updated this week
- Fabric generator and CAD tools☆163Updated last month
- ☆77Updated last year
- submission repository for efabless mpw6 shuttle☆30Updated last year
- PLL Designs on Skywater 130nm MPW☆20Updated last year