Alternatives and similar repositories for caravel_user_project:

Users that are interested in caravel_user_project are comparing it to the libraries listed below

• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• efabless / caravel_board
  ☆34Updated 5 months ago
• westonb / sky130-analog
  Analog and power building blocks for sky130 pdk
  ☆20Updated 4 years ago
• samlittlewood / caravel_carrier
  Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.
  ☆18Updated 3 years ago
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆18Updated 4 months ago
• mattvenn / openlane_summary
  ☆21Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated last year
• jazvw / chip_art
  Convert an image to a GDS format for inclusion in a zerotoasic project
  ☆13Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• vsdip / avsddac_3v3_sky130_v1
  ☆12Updated 2 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆19Updated 4 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• vsdip / rvmyth_avsddac_interface
  ☆14Updated 3 years ago
• parasgidd / avsdpll_3v3
  This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…
  ☆15Updated 3 years ago
• vsdip / vsdsram_sky130
  ☆40Updated 3 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 5 months ago
• diadatp / sky130_rf_tools
  Guides and templates for using open source RF design tools with the SkyWater SKY130 process.
  ☆19Updated 4 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆25Updated 2 months ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆27Updated 3 months ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆34Updated 2 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• dan-rodrigues / caravel_vdp_lite
  ☆19Updated 4 years ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• ucb-cs250 / caravel_fpga250
  FPGA250 aboard the eFabless Caravel
  ☆29Updated 4 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆37Updated last year
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• efabless / caravel-lite
  ☆16Updated 5 months ago
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆27Updated 3 years ago