mattvenn / caravel_user_projectLinks
Zero to ASIC group submission for MPW2
☆13Updated 5 months ago
Alternatives and similar repositories for caravel_user_project
Users that are interested in caravel_user_project are comparing it to the libraries listed below
Sorting:
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 2 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆29Updated 7 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 8 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 9 months ago
- FPGA250 aboard the eFabless Caravel☆30Updated 4 years ago
- ☆36Updated 10 months ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Wishbone interconnect utilities☆41Updated 7 months ago
- Extended and external tests for Verilator testing☆16Updated last week
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- ☆20Updated 4 years ago
- ☆17Updated 10 months ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 5 months ago
- ☆38Updated 3 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 3 years ago
- This repository contains the design and simulation process and results of potentiometric digital to analog converter.☆15Updated 4 years ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 3 years ago
- UART cocotb module☆11Updated 4 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- ☆23Updated 3 weeks ago
- sample VCD files☆37Updated this week
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 3 months ago
- A current mode buck converter on the SKY130 PDK☆30Updated 4 years ago
- ☆70Updated last year
- ☆42Updated 3 years ago