mattvenn / caravel_user_projectLinks
Zero to ASIC group submission for MPW2
☆13Updated 8 months ago
Alternatives and similar repositories for caravel_user_project
Users that are interested in caravel_user_project are comparing it to the libraries listed below
Sorting:
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Carrier for efabless Caravel chip used for Google/Skywater 130nm shuttle program.☆18Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 10 months ago
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated 4 months ago
- ☆17Updated last year
- ☆20Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated 2 years ago
- Ubuntu scripts that are used for setting up your machine for Sky130 designs.☆18Updated 4 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆14Updated 8 months ago
- ☆38Updated 3 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- Extended and external tests for Verilator testing☆17Updated 2 weeks ago
- Guides and templates for using open source RF design tools with the SkyWater SKY130 process.☆19Updated 5 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆33Updated 9 months ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆17Updated 3 years ago
- ☆38Updated last year
- Wishbone interconnect utilities☆43Updated 9 months ago
- Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.☆62Updated 4 years ago
- ☆19Updated last year
- Virtual development board for HDL design☆42Updated 2 years ago
- FPGA250 aboard the eFabless Caravel☆31Updated 4 years ago
- ☆25Updated 2 months ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- An SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop…☆12Updated 5 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- UART cocotb module☆11Updated 4 years ago