Alternatives and similar repositories for msdsl

Users that are interested in msdsl are comparing it to the libraries listed below

• sgherbst / anasymod
  A framework for FPGA emulation of mixed-signal systems
  ☆36Updated 3 years ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆45Updated 4 years ago
• bluecheetah / bag
  BAG framework
  ☆41Updated 11 months ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆39Updated 5 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 4 years ago
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆38Updated 2 years ago
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆25Updated 2 years ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆55Updated this week
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆81Updated 3 months ago
• Vlsir / Vlsir
  Interchange formats for chip design.
  ☆31Updated 2 months ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆29Updated last year
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆49Updated 5 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• idea-fasoc / fasoc
  ☆55Updated last year
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆59Updated last year
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆49Updated 2 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆33Updated 10 years ago
• google / bigspicy
  ☆41Updated 2 years ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆63Updated last week
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• bmurmann / Ngspice-on-Colab
  Sandbox for experimenting with Ngspice and open PDKs in Google Colab
  ☆23Updated last year
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆24Updated 2 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆54Updated 2 years ago
• efabless / volare
  Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
  ☆66Updated 2 weeks ago
• efabless / chipignite-resources
  ☆79Updated 2 years ago
• DDD-FIT-CTU / CMOS-SPICE-Model-Collections
  MOSIS MPW Test Data and SPICE Models Collections
  ☆37Updated 5 years ago
• ucb-art / laygo
  LAYout with Gridded Objects
  ☆29Updated 5 years ago
• RTimothyEdwards / netgen
  Netgen complete LVS tool for comparing SPICE or verilog netlists
  ☆120Updated last month
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆121Updated last year
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated last month