apertus-open-source-cinema / axiom-micro-gatewareLinks
gateware for the main fpga, including a hispi decoder and image processing
☆13Updated 7 years ago
Alternatives and similar repositories for axiom-micro-gateware
Users that are interested in axiom-micro-gateware are comparing it to the libraries listed below
Sorting:
- Verilog based simulation modell for 7 Series PLL☆17Updated 5 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45Updated 8 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Updated 2 years ago
- AXI support for Migen/MiSoC☆28Updated 7 months ago
- PicoRV☆43Updated 5 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated last month
- Small footprint and configurable JESD204B core☆50Updated last week
- lightweight open HLS for FPGA rapid prototyping☆20Updated 7 years ago
- A simple spidergon network-on-chip with wormhole switching feature☆12Updated 4 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- ☆13Updated 4 years ago
- Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.☆19Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated last week
- MMC (and derivative standards) host controller☆25Updated 5 years ago
- Using VexRiscv without installing Scala☆39Updated 4 years ago
- An alternative PnR system, or at least an attempt to get it running on Ubuntu 18.04.☆10Updated 7 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 6 months ago
- SDIO Device Verilog Core☆24Updated 7 years ago
- SDI interface board for the apertus° AXIOM beta camera☆13Updated 7 years ago
- USB 1.1 Device IP Core☆21Updated 8 years ago
- AXI Formal Verification IP☆22Updated 4 years ago
- nextpnr portable FPGA place and route tool☆11Updated 5 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Updated 5 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated 2 months ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface☆12Updated 8 years ago
- The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With stan…☆53Updated 3 weeks ago
- Small footprint and configurable HyperBus core☆14Updated 3 years ago
- RISC-V processor☆32Updated 3 years ago