apertus-open-source-cinema / axiom-micro-gateware

Related projects: ⓘ

• felixheld / AXIOM-photonSDI-hw
  SDI interface board for the apertus° AXIOM beta camera
  ☆12Updated 5 years ago
• buttercutter / noc
  A simple spidergon network-on-chip with wormhole switching feature
  ☆11Updated 3 years ago
• FeldmeierMichael / MIPI_CSI_2
  ☆12Updated last year
• nmi-leipzig / sim-x-pll
  Verilog based simulation modell for 7 Series PLL
  ☆11Updated 4 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 6 years ago
• chipsalliance / f4pga-xc7-bram-patch
  Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.
  ☆17Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆43Updated 4 years ago
• enjoy-digital / litesata_axiom
  ☆12Updated 3 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆49Updated last year
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 6 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆34Updated 2 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 4 years ago
• paulscherrerinstitute / xvcSupport
  ☆17Updated 3 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆22Updated 4 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆15Updated 2 months ago
• fusesoc / sd_device
  SD device emulator from ProjectVault
  ☆14Updated 4 years ago
• greatscottgadgets / bucatini
  a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface
  ☆31Updated 2 years ago
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 4 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆10Updated 2 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆15Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆53Updated this week
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆26Updated 2 weeks ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 2 years ago
• coltonshane / WAVE-Vivado
  HDL and C source for WAVE Zynq Ultrascale+ SoC
  ☆15Updated 2 years ago
• MightyDevices / DSITx
  FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display
  ☆18Updated 6 years ago
• gatecat / meowality
  ☆15Updated last year
• rqou / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 6 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year