SLink-Protocol / S-LinkLinks
An Open Source Link Protocol and Controller
☆25Updated 3 years ago
Alternatives and similar repositories for S-Link
Users that are interested in S-Link are comparing it to the libraries listed below
Sorting:
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- SCARV: a side-channel hardened RISC-V platform☆27Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated 3 weeks ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 4 months ago
- ☆30Updated 2 months ago
- Platform Level Interrupt Controller☆41Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆18Updated 10 months ago
- Open FPGA Modules☆23Updated 8 months ago
- AXI X-Bar☆19Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated 11 months ago
- ASIC Design of the openSPARC Floating Point Unit☆13Updated 8 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 5 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 5 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆14Updated 6 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆20Updated 3 years ago
- An Open Source Link Protocol and Controller☆27Updated 3 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- ☆33Updated 2 years ago
- ☆59Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 4 months ago
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆18Updated last month
- pulp_soc is the core building component of PULP based SoCs☆80Updated 3 months ago
- ☆14Updated 2 months ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆28Updated last year