Lichee-Pi / Tang_E203_Mini
LicheeTang 蜂鸟E203 Core
☆186Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for Tang_E203_Mini
- Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/☆110Updated 3 years ago
- OpenSource HummingBird RISC-V Software Development Kit☆143Updated 11 months ago
- OpenXuantie - OpenE902 Core☆137Updated 4 months ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆123Updated 5 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆164Updated 5 years ago
- Light-weight RISC-V RV32IMC microcontroller core.☆103Updated 7 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆129Updated 5 months ago
- LicheeTang FPGA Examples☆119Updated 4 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆67Updated 3 years ago
- riscv资料、论文等☆140Updated 6 years ago
- OpenXuantie - OpenE906 Core☆137Updated 4 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆199Updated 4 years ago
- iCESugar FPGA Board (base on iCE40UP5k)☆363Updated 2 weeks ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆99Updated 2 years ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆54Updated last year
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆114Updated 4 years ago
- Nuclei RISC-V Software Development Kit☆125Updated this week
- 8051 core☆98Updated 10 years ago
- Verilog implementation of a RISC-V core☆102Updated 6 years ago
- DEPRECATED: Please update to risc-none-elf-gcc-xpack☆114Updated last year
- The GNU MCU Eclipse RISC-V Embedded GCC☆75Updated 5 years ago
- OpenXuantie - OpenC906 Core☆323Updated 4 months ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆259Updated 4 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆107Updated 2 years ago
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆327Updated 7 years ago
- Labs to learn SpinalHDL☆144Updated 4 months ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆75Updated 4 years ago
- A port of FreeRTOS for the RISC-V ISA☆75Updated 5 years ago
- OpenRISC 1200 implementation☆161Updated 9 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago