Lichee-Pi / Tang_E203_MiniLinks
LicheeTang 蜂鸟E203 Core
☆195Updated 5 years ago
Alternatives and similar repositories for Tang_E203_Mini
Users that are interested in Tang_E203_Mini are comparing it to the libraries listed below
Sorting:
- OpenSource HummingBird RISC-V Software Development Kit☆157Updated last year
- Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/☆111Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 5 years ago
- OpenXuantie - OpenE902 Core☆147Updated 11 months ago
- OpenXuantie - OpenE906 Core☆139Updated 11 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆214Updated 4 years ago
- OpenXuantie - OpenC906 Core☆355Updated 11 months ago
- LicheeTang FPGA Examples☆122Updated 5 years ago
- Light-weight RISC-V RV32IMC microcontroller core.☆104Updated 8 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆269Updated 4 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆184Updated 5 years ago
- riscv资料、论文等☆143Updated 6 years ago
- Verilog implementation of a RISC-V core☆118Updated 6 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆72Updated 3 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆136Updated 11 months ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆107Updated 2 years ago
- Nuclei RISC-V Software Development Kit☆138Updated this week
- The GNU MCU Eclipse RISC-V Embedded GCC☆79Updated 5 years ago
- iCESugar FPGA Board (base on iCE40UP5k)☆392Updated last month
- RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.☆360Updated 7 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆467Updated 3 years ago
- Fork of OpenOCD that has RISC-V support☆483Updated last month
- Various HDL (Verilog) IP Cores☆802Updated 3 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆577Updated 9 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆320Updated 5 months ago
- WISHBONE SD Card Controller IP Core☆123Updated 2 years ago
- Labs to learn SpinalHDL☆148Updated 11 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆257Updated last month
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆127Updated 5 years ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆120Updated 2 years ago