Lichee-Pi / Tang_E203_MiniLinks
LicheeTang 蜂鸟E203 Core
☆199Updated 6 years ago
Alternatives and similar repositories for Tang_E203_Mini
Users that are interested in Tang_E203_Mini are comparing it to the libraries listed below
Sorting:
- Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/☆112Updated 4 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆196Updated 6 years ago
- OpenXuantie - OpenE902 Core☆165Updated last year
- OpenXuantie - OpenE906 Core☆151Updated last year
- OpenSource HummingBird RISC-V Software Development Kit☆167Updated 2 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Updated 6 years ago
- Light-weight RISC-V RV32IMC microcontroller core.☆104Updated 8 years ago
- Silicon-validated SoC implementation of the PicoSoc/PicoRV32☆279Updated 5 years ago
- riscv资料、论文等☆144Updated 7 years ago
- iCESugar FPGA Board (base on iCE40UP5k)☆417Updated 3 months ago
- 8051 core☆109Updated 11 years ago
- Verilog implementation of a RISC-V core☆133Updated 7 years ago
- OpenXuantie - OpenC906 Core☆380Updated last year
- SpinalHDL-tutorial based on Jupyter Notebook☆147Updated last year
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆77Updated 4 years ago
- LicheeTang FPGA Examples☆124Updated 6 years ago
- Support for Rocket Chip on Zynq FPGAs☆413Updated 6 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆221Updated 5 years ago
- ☆144Updated 5 years ago
- Nuclei RISC-V Software Development Kit☆154Updated last week
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- ☆64Updated 11 months ago
- Fork of OpenOCD that has RISC-V support☆502Updated 2 months ago
- The GNU MCU Eclipse RISC-V Embedded GCC☆78Updated 6 years ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆72Updated 2 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- A full-speed device-side USB peripheral core written in Verilog.☆235Updated 3 years ago
- WISHBONE SD Card Controller IP Core☆130Updated 3 years ago
- Verilog UART☆187Updated 12 years ago
- OpenRISC 1200 implementation☆176Updated 10 years ago