Alternatives and similar repositories for home

Users that are interested in home are comparing it to the libraries listed below

• cnrv / riscv-soc-book
  关于RISC-V你所需要知道的一切
  ☆561Updated 2 years ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆415Updated last week
• LiHao217 / RISC-V_article_paper_src
  riscv资料、论文等
  ☆143Updated 6 years ago
• ucb-bar / chisel-tutorial
  chisel tutorial exercises and answers
  ☆728Updated 3 years ago
• OSCPU / NutShell-doc
  ☆122Updated 2 years ago
• ucb-bar / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆714Updated 2 months ago
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆577Updated 9 months ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 6 years ago
• SI-RISCV / hbird-e-sdk
  Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/
  ☆111Updated 4 years ago
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆837Updated 3 weeks ago
• LvNA-system / labeled-RISC-V
  ☆169Updated 3 years ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆175Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆107Updated 2 years ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆408Updated 6 years ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,037Updated 8 months ago
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆743Updated this week
• riscvarchive / riscv-software-list
  The RISC-V software tools list, as seen on riscv.org
  ☆466Updated 4 years ago
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆636Updated last month
• riscvarchive / riscv-cores-list
  RISC-V Cores, SoC platforms and SoCs
  ☆881Updated 4 years ago
• Lichee-Pi / Tang_E203_Mini
  LicheeTang 蜂鸟E203 Core
  ☆195Updated 5 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆879Updated 2 years ago
• riscv-software-src / riscv-tools
  RISC-V Tools (ISA Simulator and Tests)
  ☆1,170Updated 2 years ago
• ljgibbslf / SM3_core
  ☆141Updated 4 years ago
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆1,077Updated last week
• pulp-platform / ara
  The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …
  ☆429Updated last week
• ridecore / ridecore
  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
  ☆360Updated 7 years ago
• riscvarchive / riscv-gcc
  ☆370Updated 2 years ago
• chipsalliance / firrtl
  Flexible Intermediate Representation for RTL
  ☆741Updated 9 months ago
• whik / e200_opensource
  The Ultra-Low Power RISC Core
  ☆48Updated 5 years ago
• soDLA-publishment / soDLA
  Chisel implementation of the NVIDIA Deep Learning Accelerator (NVDLA), with self-driving accelerated
  ☆229Updated 4 months ago