m-labs / lm32Links
LatticeMico32 soft processor
☆107Updated 11 years ago
Alternatives and similar repositories for lm32
Users that are interested in lm32 are comparing it to the libraries listed below
Sorting:
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆123Updated 9 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- An Open Source configuration of the Arty platform☆132Updated last year
- Yet Another RISC-V Implementation☆98Updated last year
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- CMod-S6 SoC☆43Updated 7 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- A wishbone controlled scope for FPGA's☆84Updated last year
- The OpenRISC 1000 architectural simulator☆74Updated 6 months ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 5 months ago
- Project X-Ray Database: XC7 Series☆73Updated 3 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 5 years ago
- MIPSfpga+ allows loading programs via UART and has a switchable clock☆111Updated 6 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆44Updated 3 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 5 years ago
- Spen's Official OpenOCD Mirror☆50Updated 8 months ago
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 7 years ago
- ☆63Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆68Updated 2 months ago
- Naive Educational RISC V processor☆90Updated last month
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Open Processor Architecture☆26Updated 9 years ago
- A FPGA core for a simple SDRAM controller.☆123Updated 4 years ago
- Core description files for FuseSoC☆124Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Wishbone controlled I2C controllers☆53Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆96Updated 5 years ago