LatticeMico32 soft processor
☆105Oct 10, 2014Updated 11 years ago
Alternatives and similar repositories for lm32
Users that are interested in lm32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated 2 years ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 4 years ago
- Pipelined DCPU-16 Verilog Implementation☆42May 30, 2012Updated 14 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Nov 1, 2020Updated 5 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆48Feb 12, 2026Updated 4 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Experiments with Cologne Chip's GateMate FPGA architecture☆19Nov 16, 2023Updated 2 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆127Jul 7, 2016Updated 9 years ago
- VHDLproc is a VHDL preprocessor☆24May 12, 2022Updated 4 years ago
- Galaksija computer for FPGA☆17Jul 6, 2025Updated 11 months ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆21Feb 27, 2024Updated 2 years ago
- ☆65Nov 16, 2013Updated 12 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 5 years ago
- SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU☆157Feb 18, 2014Updated 12 years ago
- VHDL related news.☆27Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆115Mar 24, 2025Updated last year
- Generic FIFO implementation with optional FWFT☆61May 27, 2020Updated 6 years ago
- The original high performance and small footprint system-on-chip based on Migen™☆343Jan 5, 2026Updated 5 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆74Mar 31, 2018Updated 8 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆585Jun 6, 2026Updated last week
- Open PicoBlaze Assembler☆63Oct 29, 2023Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated this week
- verilog core for ws2812 leds☆35Nov 3, 2021Updated 4 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆26Apr 8, 2026Updated 2 months ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 8 years ago
- Icarus SIMBUS☆21Nov 6, 2019Updated 6 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆130Aug 28, 2019Updated 6 years ago
- Small footprint and configurable embedded FPGA logic analyzer☆204Jun 2, 2026Updated 2 weeks ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 9 years ago
- An implementation of DisplayPort protocol for FPGAs☆310May 19, 2016Updated 10 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆48Dec 4, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Mar 12, 2026Updated 3 months ago
- Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)☆21Jan 15, 2016Updated 10 years ago
- Library for reading Xilinx .bit bitstream file headers with metadata extraction☆14Apr 7, 2026Updated 2 months ago
- An FPGA-based NetTLP adapter☆29Mar 10, 2020Updated 6 years ago
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 4 years ago
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆13Feb 9, 2019Updated 7 years ago
- HDL Obfuscator☆12May 13, 2021Updated 5 years ago