LatticeMico32 soft processor
☆105Oct 10, 2014Updated 12 years ago
Alternatives and similar repositories for lm32
Users that are interested in lm32 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Pipelined DCPU-16 Verilog Implementation☆42May 30, 2012Updated 14 years ago
- SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU☆156Feb 18, 2014Updated 12 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Sep 13, 2026Updated last month
- An Example implementation of Open Source Graphics Accelerator, (A fixed point, fixed function pipeline GPU)☆76Jun 7, 2012Updated 14 years ago
- Multi-threaded 32-bit embedded core family.☆24Jul 9, 2012Updated 14 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- The Easy 8-bit Processor☆186Jun 9, 2014Updated 12 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Nov 1, 2020Updated 6 years ago
- Lemberg is a time-predictable VLIW processor optimized for performance.☆21May 8, 2013Updated 13 years ago
- Parallel Array of Simple Cores. Multicore processor.☆101May 16, 2019Updated 7 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆128Jul 7, 2016Updated 10 years ago
- mor1kx - an OpenRISC 1000 processor IP core☆594Jun 6, 2026Updated 5 months ago
- The original high performance and small footprint system-on-chip based on Migen™☆342Jan 5, 2026Updated 10 months ago
- Open source implementation of a x86 processor☆345Apr 15, 2018Updated 8 years ago
- System on Chip toolkit for nMigen☆19Apr 29, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.☆15Dec 30, 2025Updated 10 months ago
- This is a collection of the built in libraries of the VHDPlus IDE toghether with examples. Commits will be featured in the IDE with futur…☆21Feb 27, 2024Updated 2 years ago
- Universal Advanced JTAG Debug Interface☆17May 10, 2024Updated 2 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆427Updated this week
- Milkymist MMU project☆12Dec 5, 2013Updated 12 years ago
- FPGA-based Nintendo Entertainment System Emulator☆275Jan 16, 2024Updated 2 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Sep 1, 2026Updated 2 months ago
- A Verilog HDL model of the MOS 6502 CPU☆391Apr 8, 2023Updated 3 years ago
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆48Dec 4, 2024Updated last year
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Yet Another RISC-V Implementation☆101Sep 21, 2024Updated 2 years ago
- Epiphany design verification infrastructure☆13Sep 8, 2015Updated 11 years ago
- A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…☆30Sep 30, 2025Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆49Updated this week
- An implementation of DisplayPort protocol for FPGAs☆317May 19, 2016Updated 10 years ago
- Microprogrammed 65C02-compatible FPGA Processor Core (Verilog-2001)☆56Sep 18, 2016Updated 10 years ago
- Industry standard I/O for nMigen☆12Apr 23, 2020Updated 6 years ago
- A 32-bit RISC-V soft processor☆329Jan 26, 2026Updated 9 months ago
- ZPUino HDL implementation☆92Aug 6, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- mirror of https://git.elphel.com/Elphel/vdt-plugin☆15Nov 29, 2017Updated 8 years ago
- A few tools for doing video processing on the Zybo FPGA board using VHDL☆11Jun 6, 2017Updated 9 years ago
- Based heavily on zet.aluzina.org and Terasic DE0☆18Nov 29, 2019Updated 6 years ago
- Moxie-compatible core repository☆48Aug 11, 2025Updated last year
- ☆11Mar 1, 2021Updated 5 years ago
- a playground for xilinx zynq fpga experiments☆50Nov 19, 2018Updated 7 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆52Oct 27, 2015Updated 11 years ago