Alternatives and similar repositories for lm32

Users that are interested in lm32 are comparing it to the libraries listed below

• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 2 months ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆52Updated 3 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆63Updated 7 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆93Updated 8 months ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆42Updated 7 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆130Updated last year
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆69Updated 3 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆121Updated 8 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated last week
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆65Updated 4 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆83Updated this week
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 3 months ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 2 months ago
• cambridgehackers / fpgamake
  Generates Makefiles to synthesize, place, and route verilog using Vivado
  ☆96Updated 3 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆74Updated 6 years ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 4 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆59Updated last week
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 6 years ago
• openrisc / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆32Updated 3 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆179Updated 5 months ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆88Updated 6 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆74Updated last month
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆82Updated last year
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year