micro-FPGA / engine-VLinks
SoftCPU/SoC engine-V
☆54Updated 4 months ago
Alternatives and similar repositories for engine-V
Users that are interested in engine-V are comparing it to the libraries listed below
Sorting:
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- ☆64Updated 6 years ago
- Spen's Official OpenOCD Mirror☆50Updated 4 months ago
- Naive Educational RISC V processor☆85Updated 2 weeks ago
- Yet Another RISC-V Implementation☆96Updated 10 months ago
- Demo SoC for SiliconCompiler.☆60Updated 2 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Xilinx Unisim Library in Verilog☆81Updated 5 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 4 years ago
- Wishbone interconnect utilities☆41Updated 5 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- A utility for Composing FPGA designs from Peripherals☆182Updated 7 months ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- LatticeMico32 soft processor☆106Updated 10 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated last week
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Reusable Verilog 2005 components for FPGA designs☆45Updated 5 months ago
- Bitstream relocation and manipulation tool.☆47Updated 2 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆98Updated last week
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- An Open Source configuration of the Arty platform☆130Updated last year
- Another tiny RISC-V implementation☆56Updated 4 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- Dual-issue RV64IM processor for fun & learning☆63Updated 2 years ago