Alternatives and similar repositories for engine-V

Users that are interested in engine-V are comparing it to the libraries listed below

• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆64Updated 6 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆50Updated 5 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆87Updated last month
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 11 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated this week
• m-labs / lm32
  LatticeMico32 soft processor
  ☆106Updated 10 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆91Updated 5 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆84Updated 5 years ago
• lxp32 / lxp32-cpu
  A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
  ☆61Updated 2 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆80Updated 4 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆90Updated 6 years ago
• bwitherspoon / rv32cpu
  A RISC-V processor
  ☆15Updated 6 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆58Updated 4 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆75Updated 6 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆105Updated last week
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆47Updated 2 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆131Updated last year