SoftCPU/SoC engine-V
☆56Mar 19, 2025Updated 11 months ago
Alternatives and similar repositories for engine-V
Users that are interested in engine-V are comparing it to the libraries listed below
Sorting:
- ☆64Dec 16, 2018Updated 7 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆129Aug 28, 2019Updated 6 years ago
- Provides automation scripts for building BFMs☆16Apr 19, 2025Updated 10 months ago
- RISCV SoftCPU Contest 2018☆14Nov 17, 2018Updated 7 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71May 30, 2022Updated 3 years ago
- 32-Bit RISC microprocessor system for FPGA boards☆36Nov 29, 2024Updated last year
- Small micro-coded RISC-V softcore☆15Nov 27, 2018Updated 7 years ago
- It's a CP/M 2.2 Emulator for Win32/64 and Linux☆11May 11, 2024Updated last year
- Blaze: a VT420 emulator☆30Jan 4, 2026Updated last month
- Bonfire SoC running on FireAnt FPGA Board☆12Feb 11, 2024Updated 2 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆73Apr 4, 2019Updated 6 years ago
- ☆26Sep 3, 2020Updated 5 years ago
- SERV - The SErial RISC-V CPU☆1,757Feb 19, 2026Updated last week
- ☆16Jan 25, 2026Updated last month
- ☆10Dec 28, 2020Updated 5 years ago
- A modern BLISS compiler, based on LLVM and exposing some of its useful items.☆16Oct 11, 2019Updated 6 years ago
- Open source library to handle integers of any size in C☆14Apr 11, 2023Updated 2 years ago
- Fluid Pipelines☆11May 4, 2018Updated 7 years ago
- Using VexRiscv without installing Scala☆39Nov 10, 2021Updated 4 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆82Oct 11, 2019Updated 6 years ago
- Experiments with fixed function renderers and Chisel HDL☆60Mar 31, 2019Updated 6 years ago
- RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance☆376Oct 19, 2023Updated 2 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆66May 29, 2025Updated 9 months ago
- OpenFPGA☆34Mar 12, 2018Updated 7 years ago
- A SoC for DOOM☆20Apr 11, 2021Updated 4 years ago
- OscillatorIMP ecosystem FPGA IP sources☆27Feb 22, 2026Updated last week
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102May 16, 2023Updated 2 years ago
- Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project☆17Nov 27, 2022Updated 3 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 9 years ago
- ☆18Jul 9, 2025Updated 7 months ago
- A heterogeneous architecture timing model simulator.☆174Sep 11, 2025Updated 5 months ago
- Wishbone to AXI bridge (VHDL)☆44Aug 29, 2019Updated 6 years ago
- My MEng thesis code - verifying a security property for an SoC with Rosette☆17Jun 9, 2021Updated 4 years ago
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- micropython ESP32 programmer/flasher for ECP5 JTAG☆74Sep 14, 2025Updated 5 months ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 6 years ago
- Minimal microprocessor☆21Jul 1, 2017Updated 8 years ago
- Hardware generator debugger☆77Feb 12, 2024Updated 2 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆963Nov 15, 2024Updated last year