maikmerten / spu32
Small Processing Unit 32: A compact RV32I CPU written in Verilog
☆68Updated 2 years ago
Alternatives and similar repositories for spu32:
Users that are interested in spu32 are comparing it to the libraries listed below
- SoftCPU/SoC engine-V☆54Updated last week
- Wishbone interconnect utilities☆39Updated last month
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 6 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- Yet Another RISC-V Implementation☆90Updated 6 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆85Updated 6 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- A utility for Composing FPGA designs from Peripherals☆173Updated 3 months ago
- An Open Source configuration of the Arty platform☆128Updated last year
- Verilog wishbone components☆113Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆77Updated this week
- Portable HyperRAM controller☆54Updated 3 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆39Updated last year
- Reusable Verilog 2005 components for FPGA designs☆40Updated last month
- ☆129Updated 3 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated 11 months ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆62Updated 6 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆42Updated 11 months ago
- FuseSoC standard core library☆129Updated last month
- Spen's Official OpenOCD Mirror☆48Updated 2 weeks ago
- Naive Educational RISC V processor☆79Updated 5 months ago
- A wishbone controlled scope for FPGA's☆77Updated last year
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.☆39Updated 4 years ago