maikmerten / spu32Links
Small Processing Unit 32: A compact RV32I CPU written in Verilog
☆69Updated 3 years ago
Alternatives and similar repositories for spu32
Users that are interested in spu32 are comparing it to the libraries listed below
Sorting:
- SoftCPU/SoC engine-V☆55Updated 7 months ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆80Updated 5 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- Wishbone interconnect utilities☆42Updated 8 months ago
- Basic USB 1.1 Host Controller for small FPGAs☆95Updated 5 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- Yet Another RISC-V Implementation☆98Updated last year
- Spen's Official OpenOCD Mirror☆50Updated 7 months ago
- ☆137Updated 10 months ago
- A Video display simulator☆173Updated 5 months ago
- A FPGA core for a simple SDRAM controller.☆123Updated 3 years ago
- USB Serial on the TinyFPGA BX☆136Updated 4 years ago
- Naive Educational RISC V processor☆89Updated last week
- Demo SoC for SiliconCompiler.☆61Updated 2 weeks ago
- ☆39Updated 4 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- Another tiny RISC-V implementation☆59Updated 4 years ago
- FuseSoC standard core library☆147Updated 4 months ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 6 years ago
- An Open Source configuration of the Arty platform☆133Updated last year
- A utility for Composing FPGA designs from Peripherals☆185Updated 10 months ago
- Portable HyperRAM controller☆60Updated 10 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆66Updated last week
- Reusable Verilog 2005 components for FPGA designs☆47Updated 8 months ago
- ☆63Updated 6 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆99Updated this week
- Virtual Development Board☆62Updated 3 years ago