maikmerten / spu32
Small Processing Unit 32: A compact RV32I CPU written in Verilog
☆63Updated 2 years ago
Related projects: ⓘ
- SoftCPU/SoC engine-V☆54Updated last year
- Wishbone interconnect utilities☆34Updated 3 months ago
- Featherweight RISC-V implementation☆52Updated 2 years ago
- Naive Educational RISC V processor☆69Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆84Updated 4 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆80Updated 6 years ago
- Minimal DVI / HDMI Framebuffer☆74Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆34Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆78Updated 4 years ago
- Yet Another RISC-V Implementation☆82Updated 8 months ago
- A pipelined RISC-V processor☆47Updated 9 months ago
- FPGA GPU design for DE1-SoC☆70Updated 2 years ago
- User-friendly explanation of Yosys options☆111Updated 2 years ago
- Tools for FPGA development.☆43Updated last year
- ☆37Updated 3 years ago
- Portable HyperRAM controller☆47Updated last month
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆54Updated this week
- Spen's Official OpenOCD Mirror☆45Updated 6 months ago
- Another tiny RISC-V implementation☆51Updated 3 years ago
- ☆76Updated 6 months ago
- Miscellaneous ULX3S examples (advanced)☆74Updated 10 months ago
- A FPGA core for a simple SDRAM controller.☆113Updated 2 years ago
- Nitro USB FPGA core☆82Updated 6 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆86Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆69Updated 5 months ago
- FPGA USB 1.1 Low-Speed Implementation☆32Updated 5 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆72Updated last year
- FPGA based microcomputer sandbox for software and RTL experimentation☆41Updated this week
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆58Updated 5 years ago
- A wishbone controlled scope for FPGA's☆72Updated 8 months ago