Naive Educational RISC V processor
☆99Oct 12, 2025Updated 10 months ago
Alternatives and similar repositories for nerv
Users that are interested in nerv are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Collection of test cases for Yosys☆17Jan 4, 2022Updated 4 years ago
- RISC-V Formal Verification Framework☆209Jul 15, 2026Updated 3 weeks ago
- RISCV implementation in Verilog (RV32I spec)☆17Nov 5, 2025Updated 9 months ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆55Feb 2, 2026Updated 6 months ago
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- World's first Nintendo 3DS emulator for Apple devices based on Citra.☆18Apr 7, 2023Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆73Nov 7, 2024Updated last year
- Code repository for Coppelia tool☆23Nov 12, 2020Updated 5 years ago
- A design for TinyTapeout☆19Sep 23, 2022Updated 3 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,328Jul 31, 2026Updated 2 weeks ago
- ☆25Oct 24, 2022Updated 3 years ago
- Mutation Cover with Yosys (MCY)☆96Aug 5, 2026Updated last week
- Equivalence checking with Yosys☆60Aug 5, 2026Updated last week
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆27Oct 4, 2023Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ABC: System for Sequential Logic Synthesis and Formal Verification☆34Updated this week
- A padring generator for ASICs☆26May 17, 2023Updated 3 years ago
- A RISC-V assembler library for Scala/Chisel HDL projects☆16Updated this week
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆129Nov 10, 2025Updated 9 months ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆95Nov 7, 2024Updated last year
- SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows☆538Aug 5, 2026Updated last week
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆49Jan 4, 2025Updated last year
- User-space C driver for Joulescope™ products☆16Updated this week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Atom Hardware IDE☆13May 4, 2021Updated 5 years ago
- The source code to the Voss II Hardware Verification Suite☆58Updated this week
- Verilog implementation of a simple riscv cpu☆19Oct 28, 2021Updated 4 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Aug 28, 2019Updated 6 years ago
- RISC-V CPU Core☆443Jun 24, 2025Updated last year
- RISC-V Cores, SoC platforms and SoCs☆927Mar 26, 2021Updated 5 years ago
- Repository containing ULX3S blink LED binaries☆14May 16, 2022Updated 4 years ago
- ☆61Aug 30, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- nextpnr portable FPGA place and route tool☆1,725Updated this week
- Yosys Plugins☆22Jul 16, 2019Updated 7 years ago
- SERV - The SErial RISC-V CPU☆1,859Jul 10, 2026Updated last month
- Fork of github.com/UCSBarchlab/OpenTPU for the TGPTPU project☆15Jun 1, 2025Updated last year
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆128Oct 13, 2020Updated 5 years ago
- Another tiny RISC-V implementation☆68Jul 19, 2021Updated 5 years ago