Alternatives and similar repositories for pulp-dsp:

Users that are interested in pulp-dsp are comparing it to the libraries listed below

• pulp-platform / ne16
  Neural Engine, 16 input channels
  ☆13Updated 2 years ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆15Updated 3 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆44Updated last month
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆31Updated last year
• jerry-D / 64-bit-Universal-Floating-Point-ISA-Compute-Engine
  RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine
  ☆22Updated 2 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆51Updated 2 months ago
• pulp-platform / gvsoc
  Pulp virtual platform
  ☆23Updated 2 years ago
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆19Updated 4 months ago
• sifive / block-nvdla-sifive
  ☆42Updated 3 years ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆42Updated 2 months ago
• AlSaqr-platform / he-soc
  ☆31Updated this week
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆63Updated last week
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆64Updated 7 months ago
• semidynamics / OpenVectorInterface
  Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit
  ☆34Updated 3 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆30Updated 3 months ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆32Updated last year
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆36Updated 2 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆70Updated this week
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆28Updated this week
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆34Updated 4 years ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 8 months ago
• IObundle / iob-mem
  Verilog behavioral description of various memories
  ☆30Updated 2 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆18Updated 8 months ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆21Updated 6 years ago
• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆24Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 9 months ago
• misaleh / CMSIS-DSP-PULPino
  CMSIS DSP Library for PULPino microcontroller
  ☆22Updated 6 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• Avnet / petalinux
  Repository used to support automated builds under PetaLinux tools that use Yocto.
  ☆58Updated 2 weeks ago