☆35Mar 8, 2023Updated 3 years ago
Alternatives and similar repositories for pulp-dsp
Users that are interested in pulp-dsp are comparing it to the libraries listed below
Sorting:
- ☆92Oct 18, 2023Updated 2 years ago
- Reconfigurable Binary Engine☆17Mar 23, 2021Updated 4 years ago
- ☆17Dec 19, 2025Updated 3 months ago
- ☆27Jun 12, 2022Updated 3 years ago
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆93Aug 4, 2025Updated 7 months ago
- ☆124Mar 13, 2026Updated last week
- ☆13May 10, 2018Updated 7 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- PLCT实验室 rvv-llvm 实现配套的 benchmark / testcases☆21Nov 26, 2020Updated 5 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- Direct Access Memory for MPSoC☆13Feb 28, 2026Updated 3 weeks ago
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- SystemC to Verilog Synthesizable Subset Translator☆12May 12, 2023Updated 2 years ago
- ☆103Aug 19, 2025Updated 7 months ago
- RISC-V Virtual Prototype☆46Oct 1, 2021Updated 4 years ago
- SDK for Greenwaves Technologies' GAP8 IoT Application Processor☆151May 31, 2024Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆33Jun 12, 2023Updated 2 years ago
- Neural Engine, 16 input channels☆16Oct 31, 2022Updated 3 years ago
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆196Feb 12, 2026Updated last month
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆129Aug 28, 2019Updated 6 years ago
- Verilog Code for an 8-bit ALU☆15Oct 29, 2016Updated 9 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21Jan 17, 2026Updated 2 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆237Nov 20, 2024Updated last year
- ☆16Jul 10, 2025Updated 8 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆224Jan 11, 2026Updated 2 months ago
- pulp_soc is the core building component of PULP based SoCs☆83Mar 10, 2025Updated last year
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- The Go programming language☆15Aug 27, 2018Updated 7 years ago
- ZPU - the worlds smallest 32 bit CPU with GCC toolchain☆16Jul 17, 2014Updated 11 years ago
- RISCV CPU implementation in SystemVerilog☆32Updated this week
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Nov 19, 2025Updated 4 months ago
- ☆26Jul 19, 2024Updated last year
- Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL☆15Mar 21, 2024Updated 2 years ago
- The multi-core cluster of a PULP system.☆113Mar 12, 2026Updated last week
- Fast and Efficient Deep Learning Library in C☆18Jun 3, 2022Updated 3 years ago
- Examples on how to use the GAP8 on the AI-deck☆57Sep 18, 2025Updated 6 months ago
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated last year
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Mar 9, 2026Updated last week
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,197May 26, 2025Updated 9 months ago