SonalPinto / kronosLinks
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
☆76Updated 2 years ago
Alternatives and similar repositories for kronos
Users that are interested in kronos are comparing it to the libraries listed below
Sorting:
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆78Updated last year
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆90Updated 6 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated 3 weeks ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆96Updated 9 months ago
- Demo SoC for SiliconCompiler.☆62Updated last week
- RISC-V Nox core☆71Updated 5 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆53Updated 3 weeks ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆75Updated last month
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆51Updated last year
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆44Updated last year
- 3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.☆91Updated 5 years ago
- Naive Educational RISC V processor☆93Updated 2 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆121Updated 4 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- pulp_soc is the core building component of PULP based SoCs☆81Updated 9 months ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆190Updated last week
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆124Updated 5 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 3 weeks ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆54Updated 2 years ago
- ☆121Updated 4 months ago
- Quick'n'dirty FuseSoC+cocotb example☆19Updated last year
- SoC based on VexRiscv and ICE40 UP5K☆160Updated 9 months ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- FuseSoC standard core library☆151Updated 3 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- Platform Level Interrupt Controller☆43Updated last year