Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
☆76May 15, 2023Updated 3 years ago
Alternatives and similar repositories for kronos
Users that are interested in kronos are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RISC-V microcontroller for embedded, FPGA and ASIC applications☆200Jul 19, 2026Updated 3 weeks ago
- RISCV implementation in Verilog (RV32I spec)☆17Nov 5, 2025Updated 9 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Aug 3, 2026Updated last week
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆39Feb 22, 2026Updated 5 months ago
- Flat Shade Society - Solskogen 2019 invite☆10Oct 2, 2019Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- RISC-V CPU Core☆443Jun 24, 2025Updated last year
- "Okiedokie" by Soopadoopa☆14Aug 22, 2020Updated 5 years ago
- CDL Hardware implementations; BBC microcomputer, RISC-V (numerous), frame buffers, JTAG, etc☆17Feb 20, 2020Updated 6 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆137Jul 11, 2025Updated last year
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆236Aug 25, 2020Updated 5 years ago
- A simple superscalar out-of-order RISC-V microprocessor☆253Feb 24, 2025Updated last year
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- Source for the PlayStation 2 demo "4 Edges" by The Black Lotus☆11Jul 23, 2016Updated 10 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆121Jun 18, 2026Updated last month
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- The winning Assembly Summer 2015 4k intro by Prismbeings.☆22Jun 29, 2016Updated 10 years ago
- A multi-threaded microprocessor interleaving as minimum three threads, which is pin-to-pin compatible with pulpino riscy cores☆19Jul 4, 2025Updated last year
- RSD: RISC-V Out-of-Order Superscalar Processor☆1,188Jul 15, 2026Updated 3 weeks ago
- Dual-issue RV64IM processor for fun & learning☆64Jul 4, 2023Updated 3 years ago
- Learn how to create your own 32-bit system from scratch.☆14Feb 15, 2022Updated 4 years ago
- A Reconfigurable RISC-V Core for Approximate Computing☆131May 30, 2025Updated last year
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆127Aug 28, 2019Updated 6 years ago
- VeeR EL2 Core☆343Updated this week
- Amoeba by Excess☆18Jun 7, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆992Nov 15, 2024Updated last year
- ☆11Nov 19, 2019Updated 6 years ago
- ☆11Nov 19, 2019Updated 6 years ago
- 1k by ferris and decypher☆11Jul 22, 2020Updated 6 years ago
- A sample implementation for todo-app using next.js, redux and typescript.☆20Jun 27, 2021Updated 5 years ago
- 🇲🇺 A list of cool open-source projects made in Mauritius☆12Oct 26, 2023Updated 2 years ago
- Ninjadev's new school demo "Construct" for Solskogen 2019☆13Jul 14, 2019Updated 7 years ago
- Distributed Systems Project for the 2019-2020 course of the Computer Science degree at the University of Havana, Cuba.☆12Feb 21, 2026Updated 5 months ago
- Triple Modular Redundancy☆31Sep 4, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 3 months ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆21Sep 10, 2025Updated 11 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆191Apr 4, 2026Updated 4 months ago
- Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs☆21Jun 4, 2020Updated 6 years ago
- An open-source 32-bit RISC-V soft-core processor☆49Sep 1, 2025Updated 11 months ago
- 32-bit Superscalar RISC-V CPU☆1,287Sep 18, 2021Updated 4 years ago
- ☆16Jan 12, 2021Updated 5 years ago