Alternatives and similar repositories for kronos

Users that are interested in kronos are comparing it to the libraries listed below

• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆117Updated 3 weeks ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆88Updated 6 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated last week
• aignacio / nox
  RISC-V Nox core
  ☆66Updated 2 weeks ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆90Updated 4 months ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆146Updated 2 months ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆85Updated 2 weeks ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆93Updated 4 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆60Updated 2 months ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆96Updated 10 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆73Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆159Updated 4 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆106Updated 4 years ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 4 months ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆138Updated 6 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆55Updated last month
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆93Updated 3 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆147Updated 9 months ago
• pulp-platform / register_interface
  Generic Register Interface (contains various adapters)
  ☆124Updated last month
• agra-uni-bremen / microrv32
  SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype
  ☆50Updated 9 months ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆99Updated 2 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆168Updated last week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆152Updated last month