SonalPinto / kronos
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
☆68Updated last year
Related projects ⓘ
Alternatives and complementary repositories for kronos
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆60Updated 7 months ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆62Updated this week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 5 months ago
- Naive Educational RISC V processor☆71Updated 3 weeks ago
- SpinalHDL based, FPGA Suitable RTL Implementation of RISC-V RV32. Aligned with RISC-V Virtual Prototype☆41Updated 2 weeks ago
- RISC-V Nox core☆61Updated 3 months ago
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆29Updated 4 months ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆84Updated 5 years ago
- Spen's Official OpenOCD Mirror☆47Updated 8 months ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆109Updated last year
- FuseSoC standard core library☆112Updated 3 weeks ago
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆103Updated this week
- SoC based on VexRiscv and ICE40 UP5K☆151Updated 7 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆98Updated 3 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆133Updated 4 months ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆45Updated 2 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆26Updated 3 weeks ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆67Updated 10 months ago
- Open source ISS and logic RISC-V 32 bit project☆40Updated this week
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆40Updated 11 months ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆78Updated 5 years ago
- An automatic clock gating utility☆40Updated 3 months ago
- 64-bit multicore Linux-capable RISC-V processor☆78Updated last month
- MR1 formally verified RISC-V CPU☆52Updated 5 years ago
- Demo SoC for SiliconCompiler.☆52Updated last week
- ☆57Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆85Updated 4 years ago
- Another tiny RISC-V implementation☆52Updated 3 years ago
- ☆36Updated 2 years ago