SonalPinto / kronos
Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
☆70Updated last year
Alternatives and similar repositories for kronos:
Users that are interested in kronos are comparing it to the libraries listed below
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆87Updated 5 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆83Updated last week
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 10 months ago
- RISC-V Nox core☆62Updated this week
- SoftCPU/SoC engine-V☆54Updated last week
- MR1 formally verified RISC-V CPU☆54Updated 6 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆77Updated this week
- The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH…☆38Updated this week
- pulp_soc is the core building component of PULP based SoCs☆79Updated 3 weeks ago
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆47Updated 7 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆102Updated 9 months ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- Platform Level Interrupt Controller☆37Updated 10 months ago
- ☆36Updated 2 years ago
- Easy-to-use JTAG TAP and Debug Controller core written in Verilog☆27Updated 6 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆83Updated 4 years ago
- A pipelined RISC-V processor☆54Updated last year
- FuseSoC standard core library☆129Updated 2 months ago
- Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop☆82Updated 3 weeks ago
- UNSUPPORTED INTERNAL toolchain builds☆36Updated 3 weeks ago
- Open source ISS and logic RISC-V 32 bit project☆43Updated 4 months ago
- Naive Educational RISC V processor☆79Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆62Updated 7 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Demo SoC for SiliconCompiler.☆59Updated 3 weeks ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆87Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆40Updated last year