ZipCPU / wbhyperram

Related projects ⓘ

Alternatives and complementary repositories for wbhyperram

• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• dirjud / Nitro-Parts-lib-Xilinx
  This is mainly a simulation library of xilinx primitives that are verilator compatible.
  ☆31Updated 4 months ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆20Updated last year
• gregdavill / litex-hyperram
  Standard HyperRAM core for ECP5 written in Litex/Migen
  ☆14Updated 4 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆36Updated 10 months ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆20Updated 5 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated last year
• rajesh-s / axi_cheatsheet
  A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)
  ☆26Updated 6 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆36Updated 3 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆71Updated 4 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆36Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 6 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆60Updated 3 weeks ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆36Updated 6 years ago
• Wren6991 / DOOMSoC
  A SoC for DOOM
  ☆16Updated 3 years ago
• merledu / symbiflow-magic
  This repository contains a makefile to easily install Symbiflow for the Xilinx 7 Series boards.
  ☆10Updated 3 years ago
• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆30Updated 4 years ago
• laforest / Octavo
  Verilog FPGA Parts Library. Old Octavo soft-CPU project.
  ☆73Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• warclab / idea
  iDEA FPGA Soft Processor
  ☆14Updated 8 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 6 months ago
• bobbl / rudolv
  RISC-V processor
  ☆28Updated 2 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated 6 months ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆26Updated last month
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆54Updated last month
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆19Updated last month