AleksandarKostovic / Riscy-SoCView external linksLinks
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
☆82Oct 11, 2019Updated 6 years ago
Alternatives and similar repositories for Riscy-SoC
Users that are interested in Riscy-SoC are comparing it to the libraries listed below
Sorting:
- PCB layout for my cheap FPGA HDMI experimenting board☆10Aug 21, 2014Updated 11 years ago
- There are many RISC V projects on iCE40. This one is mine.☆14Jun 25, 2020Updated 5 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- RISC-V CPU Core☆405Jun 24, 2025Updated 7 months ago
- ☆27Feb 15, 2025Updated last year
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆129Aug 28, 2019Updated 6 years ago
- Parallel Array of Simple Cores. Multicore processor.☆100May 16, 2019Updated 6 years ago
- Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL☆91Jul 29, 2019Updated 6 years ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- SoftCPU/SoC engine-V☆55Mar 19, 2025Updated 10 months ago
- A 32-bit Microcontroller featuring a RISC-V core☆160Feb 28, 2018Updated 7 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Feb 9, 2026Updated last week
- RiscyOO: RISC-V Out-of-Order Processor☆170Jul 3, 2020Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- RISC-V GPGPU☆36Mar 6, 2020Updated 5 years ago
- DTMF Receiver: Logic Synthesis and Physical Design using genus and innovus in 90nm process node☆14Dec 1, 2023Updated 2 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆26Apr 29, 2024Updated last year
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated last month
- Contains examples to start with Kactus2.☆23Aug 5, 2024Updated last year
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆91Oct 14, 2020Updated 5 years ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆682Jul 16, 2025Updated 7 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,183May 26, 2025Updated 8 months ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆244May 22, 2025Updated 8 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Oct 31, 2023Updated 2 years ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313May 25, 2023Updated 2 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Feb 10, 2026Updated last week
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Aug 23, 2019Updated 6 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆165May 11, 2023Updated 2 years ago
- PropForthV5.5 is Forth progamming environment for Parallax Propeller P8X32A microcontroller created by Sal Sanci☆11Aug 14, 2016Updated 9 years ago
- A PicoRV32 SoC for the TinyFPGA BX with peripherals designed for building games☆23Nov 15, 2018Updated 7 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆963Nov 15, 2024Updated last year
- An experimental System-on-Chip with a custom compiler toolchain.☆60Jan 2, 2020Updated 6 years ago
- Verilog for Julia☆51Apr 18, 2017Updated 8 years ago
- A utility for Composing FPGA designs from Peripherals☆186Dec 23, 2024Updated last year
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,945Jun 27, 2024Updated last year
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,008Dec 15, 2025Updated 2 months ago
- Sphinx extension for visual documentation of hardware written in HWT☆11Nov 12, 2025Updated 3 months ago
- Circuit Synthesis for Yao's Garbled Circuit by TinyGarble☆11Sep 25, 2020Updated 5 years ago