tej-chavan / Design-and-Verification-of-DDR3-Memory-ControllerLinks
The memory model was leveraged from micron.
☆22Updated 7 years ago
Alternatives and similar repositories for Design-and-Verification-of-DDR3-Memory-Controller
Users that are interested in Design-and-Verification-of-DDR3-Memory-Controller are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆57Updated last year
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆34Updated 6 years ago
- Implementation of the PCIe physical layer☆49Updated last month
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- SoC Based on ARM Cortex-M3☆32Updated 3 months ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆33Updated 3 months ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆23Updated 6 months ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆60Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- RISC-V Single-Cycle Processor Integrated With a Cache Memory System From RTL To GDS☆11Updated 11 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- AXI Interconnect☆52Updated 4 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆13Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆41Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated last week
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆25Updated last year
- ☆60Updated 2 years ago
- CORE-V MCU UVM Environment and Test Bench☆22Updated last year
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 3 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆13Updated last year