tej-chavan / Design-and-Verification-of-DDR3-Memory-ControllerLinks
The memory model was leveraged from micron.
☆24Updated 7 years ago
Alternatives and similar repositories for Design-and-Verification-of-DDR3-Memory-Controller
Users that are interested in Design-and-Verification-of-DDR3-Memory-Controller are comparing it to the libraries listed below
Sorting:
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- General Purpose AXI Direct Memory Access☆59Updated last year
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- ☆36Updated 6 years ago
- RTL code of some arbitration algorithm☆14Updated 6 years ago
- A Verilog implementation of a processor cache.☆28Updated 7 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆26Updated 7 months ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- ☆20Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆66Updated last year
- SoC Based on ARM Cortex-M3☆33Updated 4 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆40Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- AXI Interconnect☆52Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- ☆26Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆14Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆27Updated last year
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆14Updated 5 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated 2 years ago