Alternatives and similar repositories for Design-and-Verification-of-DDR3-Memory-Controller

Users that are interested in Design-and-Verification-of-DDR3-Memory-Controller are comparing it to the libraries listed below

• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆22Updated 6 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆51Updated last year
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆22Updated 4 months ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• Youssefmdany / 10-Gigabit-Ethernet-MAC-Core-UVM-Verification-
  10 Gigabit Ethernet MAC Core UVM Verification
  ☆13Updated last year
• canbozaci / Cache
  L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
  ☆12Updated 2 years ago
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆51Updated 4 years ago
• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆49Updated 3 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆16Updated 3 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆43Updated last year
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆32Updated last month
• wanderingnail / AXI_DMA
  ☆20Updated 2 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆12Updated 5 years ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆12Updated 4 years ago
• JonathanJing / Asynchronous-FIFO
  Asynchronous fifo in verilog
  ☆35Updated 9 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆56Updated last year
• Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge
  Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…
  ☆19Updated last year
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆17Updated 4 years ago
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆32Updated 2 years ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 4 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆38Updated 2 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆31Updated 3 weeks ago
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆21Updated 11 months ago