tej-chavan / Design-and-Verification-of-DDR3-Memory-ControllerLinks
The memory model was leveraged from micron.
☆22Updated 7 years ago
Alternatives and similar repositories for Design-and-Verification-of-DDR3-Memory-Controller
Users that are interested in Design-and-Verification-of-DDR3-Memory-Controller are comparing it to the libraries listed below
Sorting:
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- SoC Based on ARM Cortex-M3☆32Updated 2 weeks ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆49Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆20Updated 5 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 3 years ago
- ☆20Updated 2 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆55Updated last year
- ☆33Updated 6 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 3 months ago
- ☆25Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 4 years ago
- CORE-V MCU UVM Environment and Test Bench☆21Updated 10 months ago
- ☆21Updated 5 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆25Updated last year
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…☆16Updated last year
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆14Updated 7 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆18Updated 7 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆32Updated 2 years ago