The memory model was leveraged from micron.
☆32Mar 24, 2018Updated 8 years ago
Alternatives and similar repositories for Design-and-Verification-of-DDR3-Memory-Controller
Users that are interested in Design-and-Verification-of-DDR3-Memory-Controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 8 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆25Jul 6, 2018Updated 8 years ago
- Maven Silicon Project☆20Oct 13, 2018Updated 8 years ago
- DDR3 function verification environment in UVM☆28Apr 1, 2018Updated 8 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Designed a closed page policy memory controller following the timing specifications for DDR3 DRAM in system verilog. Was responsible for …☆11Mar 4, 2020Updated 6 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- EE577b-Course-Project☆19May 6, 2020Updated 6 years ago
- Implementation of the PCIe physical layer☆64Jul 11, 2025Updated last year
- ☆31May 11, 2021Updated 5 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy.…☆10Jul 22, 2020Updated 6 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆16Nov 4, 2022Updated 4 years ago
- Verification IP for SPI protocol☆21Jul 23, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆98Feb 28, 2018Updated 8 years ago
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆37Jul 17, 2025Updated last year
- EECS 470 Final Project☆11Apr 22, 2013Updated 13 years ago
- Verification IP for UART protocol☆26Aug 3, 2020Updated 6 years ago
- ☆13Apr 1, 2017Updated 9 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆13Aug 8, 2017Updated 9 years ago
- Detailed read disturbance (RowHammer and RowPress) characterization of six real HBM2 DRAM chips yielding 23 new observations and 8 new ta…☆12May 3, 2024Updated 2 years ago
- -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…☆26Dec 9, 2015Updated 10 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- DDR2 memory controller written in Verilog☆86Feb 28, 2012Updated 14 years ago
- SystemVerilog implementation of a Dynamically Weighted Round Robin arbiter☆14Mar 21, 2017Updated 9 years ago
- ☆11Jul 9, 2025Updated last year
- DDR4 Simulation Project in System Verilog☆47Aug 18, 2014Updated 12 years ago
- Verification IP for APB protocol☆35Sep 9, 2020Updated 6 years ago
- ⚡ Ultra-low-latency HFT platform: FPGA (14ns FIX), GPU TensorRT (<1ms ML), lock-free, DPDK. 350ns latency, 500K orders/sec. Production-re…☆17Nov 26, 2025Updated 11 months ago
- ☆84Feb 4, 2021Updated 5 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆94Mar 21, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- An MPEG2 video decoder, written in Verilog and implemented in an FPGA chip.☆27Apr 24, 2019Updated 7 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆646Oct 10, 2021Updated 5 years ago
- A real-time image acquisition system based on autonomous SDRAM, using automatic read-write FIFO and VGA drivers☆11Feb 7, 2023Updated 3 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆121Jul 2, 2023Updated 3 years ago
- Verilog SDRAM memory controller☆389May 13, 2017Updated 9 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 10 years ago
- ☆14Feb 1, 2025Updated last year