Reindeer Soft CPU for Step CYC10 FPGA board
☆27Dec 2, 2020Updated 5 years ago
Alternatives and similar repositories for Reindeer_Step
Users that are interested in Reindeer_Step are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PulseRain RISC-V board manager package for Arduino IDE☆13Mar 15, 2022Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Aug 28, 2019Updated 7 years ago
- Deprecated, no longer updated, please change to https://www.nucleisys.com/index.php☆25Mar 24, 2021Updated 5 years ago
- turbo 8051☆31Aug 30, 2017Updated 9 years ago
- ☆13Jun 9, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- awtk books and manuals☆13Feb 14, 2022Updated 4 years ago
- asr6501 SDK 适配lorawan 发起人：张俊☆10Jan 14, 2021Updated 5 years ago
- Machine Learning with TensorFlow 1.x, published by Packt☆15Mar 2, 2026Updated 7 months ago
- IP cores for the FPGA Libre project☆12Aug 7, 2017Updated 9 years ago
- ☆19Sep 6, 2026Updated last month
- Simple Inertial Navigation System implementation by pure C☆13Nov 2, 2019Updated 6 years ago
- Docs of Maixduino☆13Jul 16, 2020Updated 6 years ago
- Blender 3D printing by example, published by Packt☆15Jan 18, 2023Updated 3 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆13Nov 27, 2018Updated 7 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- WISHBONE Builder☆15Sep 10, 2016Updated 10 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13May 5, 2015Updated 11 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆20Aug 9, 2026Updated 2 months ago
- Example code in Verilog for the Blackice II FPGA☆33Sep 8, 2019Updated 7 years ago
- A 32-bit RISC-V processor for mriscv project☆63Jul 17, 2017Updated 9 years ago
- Advanced IDE for developing MicroPython app with ESP8266 board☆12Mar 15, 2017Updated 9 years ago
- http://os.cs.tsinghua.edu.cn/research/undergraduate/zwpu2019☆12Jun 7, 2019Updated 7 years ago
- Smart On-Chip Debugger☆23Jun 14, 2023Updated 3 years ago
- Devotes to open source FPGA☆28May 9, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆13Jun 30, 2024Updated 2 years ago
- Implemetation of pipelined ARM7TDMI processor in Verilog☆98Apr 19, 2018Updated 8 years ago
- 基于RT-Thread Studio快速完成的桌面mini时钟项目☆13Feb 21, 2020Updated 6 years ago
- Mostly AVR compatible FPGA soft-core☆30Sep 30, 2021Updated 5 years ago
- Deprecated, please go to https://github.com/riscv-mcu/hbird-sdk/☆115Mar 24, 2021Updated 5 years ago
- ☆11Jan 8, 2021Updated 5 years ago
- ☆14Oct 19, 2019Updated 6 years ago
- Source of Feitian OpenSK USB Dongle help docs.☆11Jul 5, 2022Updated 4 years ago
- asr6505 sdk，支持标准lorwan协议。☆18Jan 14, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- StudyLive是anyRTC开发的示例项目，演示了如何通过anyRTC云服务，配合anyRTC RTC SDK、anyRTC RTM SDK、anyRTC播放插件，实现在线自习室的场景。☆17Aug 12, 2022Updated 4 years ago
- Generic AXI master stub☆20Jul 17, 2014Updated 12 years ago
- An Arduino UNO compatible implementation for the iCE40 FPGAs☆20Oct 7, 2020Updated 6 years ago
- ☆12Dec 8, 2017Updated 8 years ago
- emulator for ARM☆11Jun 14, 2019Updated 7 years ago
- awtk-aworks-rt1052☆33Dec 13, 2021Updated 4 years ago