AXI4-Compatible Verilog Cores, along with some helper modules.
☆17Mar 14, 2020Updated 6 years ago
Alternatives and similar repositories for AxiCores
Users that are interested in AxiCores are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog network module. Models network traffic from pcap to AXI-Stream☆24Apr 24, 2021Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆25Nov 7, 2018Updated 7 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 5 years ago
- A simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog t…☆16Aug 29, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- 标准视频时序生成器☆10Feb 9, 2020Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆36Mar 9, 2017Updated 9 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆88Oct 6, 2022Updated 3 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 8 years ago
- A pipelined MIPS-Lite CPU implementation☆22Dec 15, 2009Updated 16 years ago
- OscillatorIMP ecosystem FPGA IP sources☆28Feb 22, 2026Updated 4 months ago
- TCL framework to package Vivado IP-Cores☆14May 18, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A C++ template library for FPGAs on top of Xilinx Vivado HLS☆14Feb 2, 2017Updated 9 years ago
- A simple UVM example with DPI☆47Aug 7, 2017Updated 8 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 4 months ago
- Implementation of a RISC-V CPU in Verilog.☆17Jun 27, 2026Updated last week
- ☆20Jun 18, 2022Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆63Dec 31, 2019Updated 6 years ago
- git clone of http://code.google.com/p/axi-bfm/☆18May 21, 2013Updated 13 years ago
- FPGA for uSDR☆23Apr 18, 2026Updated 2 months ago
- SDRAM controller with AXI4 interface☆105Aug 8, 2019Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Verilog Repository for GIT☆36May 4, 2021Updated 5 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Jan 22, 2025Updated last year
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆18Oct 19, 2024Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- ☆26Feb 26, 2024Updated 2 years ago
- DSP by FPGA☆15Sep 12, 2023Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆106Sep 20, 2020Updated 5 years ago
- Verilog RTL Implementation of DNN☆10Jun 26, 2018Updated 8 years ago
- Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022☆11Sep 21, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- TCP/IP and UDP/IP protocol stack off-loading☆19Aug 9, 2020Updated 5 years ago
- This project shows how to use Raptor codes to provide FEC protection for H.264 video data in GNURadio and USRP board.☆13Apr 20, 2015Updated 11 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆130Aug 28, 2019Updated 6 years ago
- SCARV: a side-channel hardened RISC-V platform☆28Jan 11, 2023Updated 3 years ago
- Imaging application using MIPI and DisplayPort to process image☆25Feb 13, 2020Updated 6 years ago
- NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…☆31Feb 6, 2023Updated 3 years ago
- RV32I Single Cycle Processor (CPU)☆12Nov 14, 2021Updated 4 years ago