Cognoscan / AxiCoresLinks
AXI4-Compatible Verilog Cores, along with some helper modules.
☆16Updated 5 years ago
Alternatives and similar repositories for AxiCores
Users that are interested in AxiCores are comparing it to the libraries listed below
Sorting:
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆30Updated 9 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 8 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- LIS Network-on-Chip Implementation☆31Updated 9 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated 8 months ago
- Generic AXI master stub☆19Updated 11 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated 9 months ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆30Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆22Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 9 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆39Updated 4 years ago
- Testbenches for HDL projects☆20Updated last week
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- SystemVerilog Logger☆18Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- ☆29Updated last week
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- Advanced Debug Interface☆15Updated 8 months ago
- ☆21Updated 5 years ago
- ☆21Updated 5 years ago
- ☆16Updated 6 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated last month
- Simple demo showing how to use the ping pong FIFO☆15Updated 9 years ago
- WISHBONE Interconnect☆11Updated 8 years ago
- ASIC Design of the openSPARC Floating Point Unit☆14Updated 8 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆34Updated 4 months ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆19Updated 4 years ago