RPTU-EIS / upec-boom-verification-suite
This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.
☆17Updated 2 years ago
Alternatives and similar repositories for upec-boom-verification-suite:
Users that are interested in upec-boom-verification-suite are comparing it to the libraries listed below
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆17Updated 5 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆80Updated last year
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last month
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆53Updated 3 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆25Updated last year
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆15Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆63Updated 9 months ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆22Updated 6 years ago
- Platform Level Interrupt Controller☆38Updated 10 months ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- The RTL source for AnyCore RISC-V☆32Updated 3 years ago
- ☆32Updated 2 weeks ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆61Updated 5 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆56Updated last week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆69Updated 2 weeks ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…☆33Updated last month
- HLS for Networks-on-Chip☆33Updated 4 years ago
- ☆29Updated 3 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Advanced Architecture Labs with CVA6☆56Updated last year
- BlackParrot on Zynq☆37Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆38Updated 2 years ago
- Unit tests generator for RVV 1.0☆80Updated this week
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 3 months ago
- RISC-V Matrix Specification☆20Updated 4 months ago