RPTU-EIS / upec-boom-verification-suite
This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.
☆15Updated last year
Related projects ⓘ
Alternatives and complementary repositories for upec-boom-verification-suite
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆73Updated 7 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- Advanced Architecture Labs with CVA6☆49Updated 10 months ago
- zero-riscy CPU Core☆14Updated 6 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆62Updated 4 months ago
- ☆67Updated 10 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 8 months ago
- HLS for Networks-on-Chip☆31Updated 3 years ago
- ☆25Updated 4 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Updated 4 years ago
- Project repo for the POSH on-chip network generator☆43Updated last year
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆14Updated 3 weeks ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- An example of using Ramulator as memory model in a cycle-accurate SystemC Design☆46Updated 7 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆57Updated last year
- SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol☆17Updated 3 weeks ago
- A verilog implementation for Network-on-Chip☆67Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- ☆76Updated 8 months ago
- ☆22Updated 5 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆39Updated 4 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- Original test vector of RISC-V Vector Extension☆11Updated 3 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆49Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆59Updated this week
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆23Updated 7 months ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆56Updated 4 years ago