RPTU-EIS / upec-boom-verification-suiteLinks
This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.
β17Updated 2 years ago
Alternatives and similar repositories for upec-boom-verification-suite
Users that are interested in upec-boom-verification-suite are comparing it to the libraries listed below
Sorting:
- Microarchitectural control flow integrity (πCFI) verification checks whether there exists a control or data flow from instruction's opeβ¦β13Updated 3 months ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations madeβ¦β83Updated last year
- SystemVerilog Functional Coverage for RISC-V ISAβ28Updated this week
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operatβ¦β17Updated 7 months ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assemblyβ15Updated 4 years ago
- A Modular Open-Source Hardware Fuzzing Frameworkβ33Updated 3 years ago
- DUTH RISC-V Microprocessorβ20Updated 6 months ago
- Andes Vector Extension support added to riscv-dvβ17Updated 5 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuitsβ34Updated 4 months ago
- Advanced Architecture Labs with CVA6β61Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).β56Updated this week
- DUTH RISC-V Superscalar Microprocessorβ31Updated 7 months ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesisβ52Updated 5 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.β53Updated last month
- Project repo for the POSH on-chip network generatorβ46Updated 2 months ago
- β27Updated 5 years ago
- YosysHQ SVA AXI Propertiesβ39Updated 2 years ago
- RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute fβ¦β37Updated 3 weeks ago
- The RTL source for AnyCore RISC-Vβ32Updated 3 years ago
- Branch Predictor Optimization for BlackParrotβ15Updated last year
- β33Updated 2 months ago
- ILA Model Databaseβ22Updated 4 years ago
- Source files to reproduce the results shown for A-QED at DAC 2020β9Updated 4 years ago
- HLS for Networks-on-Chipβ34Updated 4 years ago
- IOPMP IPβ18Updated 2 weeks ago
- β30Updated 5 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platformβ19Updated 3 months ago
- BlackParrot on Zynqβ41Updated 3 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV coresβ77Updated this week
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our gβ¦β28Updated last year