RPTU-EIS / upec-boom-verification-suite
This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.
☆17Updated 2 years ago
Alternatives and similar repositories for upec-boom-verification-suite:
Users that are interested in upec-boom-verification-suite are comparing it to the libraries listed below
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆76Updated 11 months ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆16Updated 4 months ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- Tests for example Rocket Custom Coprocessors☆70Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 5 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated 2 weeks ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆47Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆13Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated last week
- ☆78Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- The RTL source for AnyCore RISC-V☆31Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 8 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆37Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Chisel implementation of AES☆23Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 4 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆20Updated 5 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 6 months ago
- ☆20Updated 5 years ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆48Updated 3 years ago
- Running Linux on IOb-SoC-OpenCryptoHW☆14Updated 6 months ago
- Coarse Grained Reconfigurable Array☆19Updated last month
- ILA Model Database☆22Updated 4 years ago
- Platform Level Interrupt Controller☆36Updated 9 months ago
- educational microarchitectures for risc-v isa☆66Updated 6 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated last month
- zero-riscy CPU Core☆16Updated 6 years ago