gtcasl / cash
A C++ Library for Hardware Design and Simulation
☆15Updated 4 years ago
Related projects: ⓘ
- firrtlator is a FIRRTL C++ library☆21Updated 7 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- RISC-V GPGPU☆34Updated 4 years ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆30Updated 9 years ago
- An open-source custom cache generator.☆25Updated 6 months ago
- A Verilog Synthesis Regression Test☆33Updated 6 months ago
- A powerful and modern open-source architecture description language.☆40Updated 6 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- The specification for the FIRRTL language☆39Updated last week
- netlistDB - Intermediate format for digital hardware representation with graph database API☆29Updated 3 years ago
- The BERI and CHERI processor and hardware platform☆45Updated 7 years ago
- Languages, Tools, and Techniques for Accelerator Design☆32Updated 2 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆35Updated 10 months ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆26Updated last week
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆22Updated 6 years ago
- FPGA Assembly (FASM) Parser and Generator☆88Updated 2 years ago
- Debuggable hardware generator☆66Updated last year
- TestFloat release 3☆51Updated 7 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆42Updated last year
- A fault-injection framework using Chisel and FIRRTL☆33Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 4 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆72Updated 5 years ago
- Documentation for the BOOM processor☆47Updated 7 years ago
- Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)☆35Updated 3 years ago
- IRSIM switch-level simulator for digital circuits☆30Updated 4 months ago
- Open Processor Architecture☆26Updated 8 years ago
- ⛔ DEPRECATED ⛔ HERO Software Development Kit☆20Updated 2 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated last year
- Benchmarks for Yosys development☆21Updated 4 years ago
- Consistency checker for memory subsystem traces☆11Updated 7 years ago