Alternatives and similar repositories for pir:

Users that are interested in pir are comparing it to the libraries listed below

• ucb-bar / cva6-wrapper
  Wrapper for ETH Ariane Core
  ☆19Updated 3 weeks ago
• firesim / icenet
  Network components (NIC, Switch) for FireBox
  ☆16Updated 5 months ago
• ucb-bar / barstools
  Useful utilities for BAR projects
  ☆31Updated last year
• stanford-ppl / argon
  Scala staging framework
  ☆16Updated 6 years ago
• fpgasystems / fpga-hyperloglog
  FPGA-based HyperLogLog Accelerator
  ☆12Updated 4 years ago
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆34Updated 2 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• CMU-SAFARI / NOCulator
  NOCulator is a network-on-chip simulator providing cycle-accurate performance models for a wide variety of networks (mesh, torus, ring, h…
  ☆23Updated 2 years ago
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆31Updated 10 years ago
• CMU-SAFARI / SMASH
  SMASH is a hardware-software cooperative mechanism that enables highly-efficient indexing and storage of sparse matrices. The key idea of…
  ☆16Updated 4 years ago
• stanford-ppl / spatial-lang
  Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
  ☆101Updated 6 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆31Updated this week
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆153Updated 7 months ago
• DFiantHDL / DFHDL
  DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
  ☆84Updated this week
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 4 years ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆100Updated 5 years ago
• Chlorophytus / broccoli
  A soft multimedia/graphics processor prototype in Chisel 3
  ☆11Updated last year
• freechipsproject / firrtl-interpreter
  A scala based simulator for circuits described by a LoFirrtl file
  ☆47Updated 2 years ago
• FelixWinterstein / FPGA-shared-mem
  Exploring Shared Virtual Memory Abstractions in OpenCL Tools for FPGAs
  ☆18Updated 7 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆21Updated last week
• Twine-Umich / Twine
  ☆10Updated 3 years ago
• stanford-ppl / spatial-multiverse
  Provides Spatial with front-end support from popular machine learning frameworks
  ☆33Updated 5 years ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆79Updated 3 months ago
• stanford-ppl / spatial-quickstart
  Quickstart for Spatial language
  ☆34Updated 4 years ago
• ucb-bar / esp-isa-sim
  Custom extensions to the RISC-V isa simulator for the UCB-BAR ESP project
  ☆17Updated 2 years ago
• RCSL-HKUST / heterosim
  HeteroSim is a full system simulator supporting x86 multicore processors combined with a FPGA via bus-based architecture. Flexible design…
  ☆21Updated 8 years ago
• freechipsproject / chisel-coverage
  A coverage library for Chisel designs
  ☆11Updated 5 years ago
• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 8 years ago
• sstsimulator / sst-tutorials
  Tutorial Material from the SST Team
  ☆19Updated 10 months ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago