Alternatives and similar repositories for CocotbLib

Users that are interested in CocotbLib are comparing it to the libraries listed below

• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆26Updated 4 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆37Updated 2 months ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated last year
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 9 months ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆41Updated 2 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated 2 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 2 months ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆19Updated 2 years ago
• edaa-org / pyEDAA.UCIS
  Unified Coverage Interoperability Standard (UCIS)
  ☆14Updated this week
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 8 months ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆17Updated this week
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 7 months ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆13Updated 9 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆30Updated last year
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆29Updated 3 months ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆16Updated last week
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆45Updated last week
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆54Updated 2 months ago
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆27Updated 9 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 3 months ago