FredKellerman / pynq-juliabrotLinks
☆19Updated 10 months ago
Alternatives and similar repositories for pynq-juliabrot
Users that are interested in pynq-juliabrot are comparing it to the libraries listed below
Sorting:
- PYNQ-ZU, AUP UltraScale+ MPSoC academic board☆27Updated 3 weeks ago
 - Introductory examples for using PYNQ with Alveo☆52Updated 2 years ago
 - PACoGen: Posit Arithmetic Core Generator☆75Updated 6 years ago
 - Open-Source HLS Examples for Microchip FPGAs☆48Updated 3 months ago
 - Universal number Posit HDL Arithmetic Architecture generator☆64Updated 6 years ago
 - ☆80Updated last week
 - Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆29Updated 7 months ago
 - The Strathclyde RFSoC Studio Installer for PYNQ.☆33Updated 2 years ago
 - PYNQ Composabe Overlays☆73Updated last year
 - ☆19Updated 4 years ago
 - A Vivado HLS Command Line Helper Tool☆36Updated 4 years ago
 - Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
 - Networking Overlay on PYNQ☆50Updated 6 years ago
 - Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago
 - hardware library for hwt (= ipcore repo)☆43Updated 2 weeks ago
 - An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆96Updated this week
 - A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Updated 3 years ago
 - BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 9 months ago
 - Posit Arithmetic Cores generated with FloPoCo☆26Updated last year
 - Blazingly fast, modern C++ API using coroutines for efficient RTL verification and co-simulation via the VPI interface☆17Updated 3 weeks ago
 - Falcon Merlin Compiler☆41Updated 5 years ago
 - Fast inference of Boosted Decision Trees in FPGAs☆57Updated last week
 - An RFSoC Frequency Planner developed using Python.☆31Updated 2 years ago
 - Xilinx Unisim Library in Verilog☆86Updated 5 years ago
 - FPGA acceleration of arbitrary precision floating point computations.☆40Updated 3 years ago
 - IEEE 754 single and double precision floating point library in systemverilog and vhdl☆72Updated 10 months ago
 - Train and deploy LUT-based neural networks on FPGAs☆100Updated last year
 - Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆102Updated 9 months ago
 - Vitis Model Composer Examples and Tutorials☆107Updated last week
 - OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆72Updated last year