Alternatives and similar repositories for pynq-juliabrot

Users that are interested in pynq-juliabrot are comparing it to the libraries listed below

• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆40Updated 3 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆75Updated 5 years ago
• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆62Updated 6 years ago
• Xilinx / PYNQ-ZU
  PYNQ-ZU, AUP UltraScale+ MPSoC academic board
  ☆26Updated this week
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• JennySmith888 / 100GBE-PYNQ
  ☆19Updated 3 years ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆45Updated last month
• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆62Updated 6 months ago
• falconcomputing / merlin-compiler
  Falcon Merlin Compiler
  ☆41Updated 5 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆32Updated 2 years ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆43Updated 2 years ago
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• V0XNIHILI / parametrizable-floating-point-verilog
  Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent
  ☆28Updated 4 months ago
• drichmond / HOPS
  Synthesizable Higher-Order Functions (Patterns) for C++
  ☆17Updated 6 years ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆49Updated 6 years ago
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• FPGA4HEP / course_material
  ☆34Updated 5 years ago
• RaulMurillo / Flo-Posit
  Posit Arithmetic Cores generated with FloPoCo
  ☆25Updated last year
• pulp-platform / redmule
  ☆73Updated last week
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆48Updated last year
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 3 years ago
• maltevesper / JetStream-hardware
  ☆22Updated 9 years ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆90Updated 7 months ago
• KastnerRG / Spector-HLS
  Contains FPGA benchmarks for Vivado HLS and Catapult HLS
  ☆26Updated 5 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆87Updated 2 months ago
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆39Updated 3 years ago
• cornell-brg / lizard
  Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
  ☆88Updated 6 years ago