Alternatives and similar repositories for pynq-juliabrot

Users that are interested in pynq-juliabrot are comparing it to the libraries listed below

• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆51Updated 2 years ago
• spcl / apfp
  FPGA acceleration of arbitrary precision floating point computations.
  ☆41Updated 3 years ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆75Updated 6 years ago
• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆32Updated 2 years ago
• Xilinx / PYNQ-Networking
  Networking Overlay on PYNQ
  ☆49Updated 6 years ago
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 3 years ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆91Updated 8 months ago
• thesps / conifer
  Fast inference of Boosted Decision Trees in FPGAs
  ☆55Updated 2 weeks ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆46Updated last month
• Xilinx / PYNQ_Composable_Pipeline
  PYNQ Composabe Overlays
  ☆73Updated last year
• Xilinx / gemx
  Matrix Operation Library for FPGA https://xilinx.github.io/gemx/
  ☆63Updated 5 years ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆71Updated last year
• chipsalliance / fpga-interchange-schema
  ☆56Updated 3 years ago
• JennySmith888 / 100GBE-PYNQ
  ☆19Updated 3 years ago
• xupgit / compute_acceleration
  ☆12Updated 5 years ago
• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆65Updated 7 months ago
• hdl / conda-eda
  Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.
  ☆102Updated 7 months ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆49Updated 2 years ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆98Updated last year
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆107Updated 7 years ago
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆30Updated 5 years ago
• Xilinx / PYNQ-ZU
  PYNQ-ZU, AUP UltraScale+ MPSoC academic board
  ☆27Updated 3 weeks ago
• maltanar / rosetta
  Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ
  ☆33Updated 6 years ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆86Updated 3 months ago
• FPGA4HEP / course_material
  ☆34Updated 5 years ago
• pulp-platform / redmule
  ☆73Updated this week
• template-hls / template-hls-float
  ☆30Updated 6 years ago
• qleenju / PDPU
  PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications
  ☆43Updated 2 years ago
• fserre / SGen
  SGen is a generator capable of producing efficient hardware designs operating on streaming datasets. “Streaming” means that the dataset i…
  ☆23Updated 3 years ago
• manish-kj / Posit-HDL-Arithmetic
  Universal number Posit HDL Arithmetic Architecture generator
  ☆63Updated 6 years ago