CoffeeBeforeArch / cache_simulatorLinks
A simple trace-based cache simulator
☆16Updated last year
Alternatives and similar repositories for cache_simulator
Users that are interested in cache_simulator are comparing it to the libraries listed below
Sorting:
- A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written …☆15Updated 8 years ago
- Example code for Modern SystemC using Modern C++☆69Updated 3 years ago
- Lab assignments for the Agile Hardware Design course☆18Updated 2 months ago
- Brief SystemC getting started tutorial☆96Updated 6 years ago
- The University of Bristol HPC Simulation Engine☆104Updated 5 months ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Updated 2 weeks ago
- RISC-V Zve32x, Zve32f, Zvfh Vector Coprocessor☆16Updated last week
- X86 CPU topics overview for developers , oriented towards performance☆204Updated last month
- The gem5 Bootcamp 2022 environment. Archived.☆36Updated last year
- Slides from the "Bits of Architecture" series on YouTube☆28Updated 3 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
- A simple C++ CMake project to jump-start development of SystemC models and systems☆30Updated last year
- Readings in Computer Architectures☆17Updated last month
- A textbook on system on chip design using Arm Cortex-A☆42Updated 7 months ago
- SystemC training aimed at TLM.☆35Updated 5 years ago
- ☆124Updated 2 years ago
- RTL data structure☆60Updated last month
- Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0☆26Updated 3 years ago
- ☆14Updated this week
- ☆22Updated 2 years ago
- A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code☆141Updated last week
- Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research☆17Updated 2 years ago
- Extremely Simple Microbenchmarks☆39Updated 7 years ago
- ☆21Updated 6 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 3 weeks ago
- ☆17Updated 3 years ago
- Parendi: Thousand-way Parallel RTL Simulation on the Graphcore IPU☆25Updated 2 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Updated 10 months ago
- The gem5-X open source framework (based on the gem5 simulator)☆42Updated 2 years ago
- RISC-V Virtual Prototype☆46Updated 4 years ago