cs-jsi / chisel4mlLinks
☆18Updated 8 months ago
Alternatives and similar repositories for chisel4ml
Users that are interested in chisel4ml are comparing it to the libraries listed below
Sorting:
- NeuraLUT-Assemble☆41Updated last month
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆48Updated 4 years ago
- Train and deploy LUT-based neural networks on FPGAs☆99Updated last year
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆25Updated 6 years ago
- Contains FPGA benchmarks for Vivado HLS and Catapult HLS☆26Updated 5 years ago
- Open-Source HLS Examples for Microchip FPGAs☆48Updated 3 months ago
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- ☆87Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆61Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆92Updated this week
- Posit Arithmetic Cores generated with FloPoCo☆26Updated last year
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆30Updated 11 months ago
- A tool to generate optimized hardware files for univariate functions.☆28Updated last year
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆43Updated last month
- ☆63Updated 5 months ago
- ☆20Updated 5 years ago
- ☆59Updated 5 years ago
- Fast inference of Boosted Decision Trees in FPGAs☆56Updated 2 weeks ago
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆91Updated 9 months ago
- DASS HLS Compiler☆29Updated 2 years ago
- Example code for Modern SystemC using Modern C++☆66Updated 2 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 4 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆35Updated last year
- Next generation CGRA generator☆115Updated this week
- sram/rram/mram.. compiler☆42Updated 2 years ago
- PYNQ Composabe Overlays☆73Updated last year
- ☆17Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆88Updated last year
- Public release☆56Updated 6 years ago