5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
☆14Dec 4, 2025Updated 7 months ago
Alternatives and similar repositories for RISCV-Core
Users that are interested in RISCV-Core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆24Mar 2, 2023Updated 3 years ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- RISC-V 64 CPU☆10Oct 4, 2025Updated 9 months ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 6 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- 中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程☆30May 30, 2020Updated 6 years ago
- HITSZ 404 NOT FOUND NSCSCC22 project☆17Sep 8, 2022Updated 3 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆16Nov 23, 2018Updated 7 years ago
- SystemVerilog implemention of the TAGE branch predictor☆14May 26, 2021Updated 5 years ago
- Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown …☆15Jan 17, 2025Updated last year
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- A small Neural Network Processor for Edge devices.☆20Nov 22, 2022Updated 3 years ago
- 5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set☆10Sep 15, 2022Updated 3 years ago
- risc-v 单周期和流水线cpu设计， 基于miniRV-1指令集，语言verilog☆11Feb 23, 2023Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆17Apr 12, 2020Updated 6 years ago
- simple 4-BIT CPU with 74-serials chip，origin by Kaoru Tonami in his book “How to build a CPU”☆14Oct 19, 2024Updated last year
- ☆16Jul 14, 2024Updated 2 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 8 months ago
- A project for learning RISC-V architecture purpose☆27Nov 9, 2023Updated 2 years ago
- Three-phase inverter operating at AC100V.☆20Oct 8, 2023Updated 2 years ago
- ☆67Aug 5, 2024Updated last year
- Community-driven open-source fuel price tracker app for Norway☆16Updated this week
- [UAV] - [STM32F103] - 6 Axes sensor MPU6050 - Quaternion & Euler Angles Compute - PID Controller☆13Oct 17, 2016Updated 9 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- ☆27Sep 3, 2020Updated 5 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- ☆22Nov 25, 2023Updated 2 years ago
- A Custom STM32 board that runs on a battery with MCP73831 and is easily programmable with USB thanks to the CP2102 USB-to-UART chip.☆13Dec 21, 2023Updated 2 years ago
- This is a set of python codes that forecast electricity price in wholesale power markets using an integrated long-term recurrent convolut…☆16Oct 14, 2022Updated 3 years ago
- This is an assignment for Pattern Recognition Course taught at Alexandria University, Faculty of Engineering offered in Spring 2019. The…☆19Jul 19, 2019Updated 7 years ago
- Pipelined 64-bit RISC-V core☆17Mar 7, 2024Updated 2 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆14Aug 1, 2024Updated last year
- A cutting-edge AI-powered health diagnosis chatbot that leverages machine learning to interpret symptoms and predict potential medical co…☆15Mar 8, 2024Updated 2 years ago
- ☆14Apr 29, 2025Updated last year
- ☆32Apr 10, 2026Updated 3 months ago
- Linux capable RISC-V SoC designed to be readable and useful.☆162Dec 19, 2025Updated 7 months ago
- Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.☆23Aug 5, 2025Updated 11 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21May 12, 2025Updated last year