5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
☆16Dec 4, 2025Updated 10 months ago
Alternatives and similar repositories for RISCV-Core
Users that are interested in RISCV-Core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆24Mar 2, 2023Updated 3 years ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- ☆10May 21, 2021Updated 5 years ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 6 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆16Nov 23, 2018Updated 7 years ago
- SystemVerilog implemention of the TAGE branch predictor☆15May 26, 2021Updated 5 years ago
- Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown …☆15Jan 17, 2025Updated last year
- 5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set☆10Sep 15, 2022Updated 4 years ago
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- risc-v 单周期和流水线cpu设计, 基于miniRV-1指令集,语言verilog☆11Feb 23, 2023Updated 3 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated 2 years ago
- only display GPU☆10Mar 6, 2025Updated last year
- ☆17Jul 14, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A project for learning RISC-V architecture purpose☆26Nov 9, 2023Updated 2 years ago
- A small Neural Network Processor for Edge devices.☆20Nov 22, 2022Updated 3 years ago
- ☆27Sep 3, 2020Updated 6 years ago
- simple 4-BIT CPU with 74-serials chip,origin by Kaoru Tonami in his book “How to build a CPU”☆15Oct 19, 2024Updated 2 years ago
- ☆68Aug 5, 2024Updated 2 years ago
- Three-phase inverter operating at AC100V.☆20Oct 8, 2023Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆24Nov 24, 2025Updated 11 months ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- [UAV] - [STM32F103] - 6 Axes sensor MPU6050 - Quaternion & Euler Angles Compute - PID Controller☆13Oct 17, 2016Updated 10 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- A real-time image acquisition system based on autonomous SDRAM, using automatic read-write FIFO and VGA drivers☆11Feb 7, 2023Updated 3 years ago
- ☆12Jun 24, 2023Updated 3 years ago
- LLM-Assisted FPGA Design for Carrier Frequency Offset Estimation☆11Sep 5, 2025Updated last year
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆15Apr 18, 2024Updated 2 years ago
- Towards an Automated Triple Modular Redundancy (TMR) EDA flow for Yosys.☆12Aug 17, 2026Updated 2 months ago
- ☆12Dec 3, 2022Updated 3 years ago
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 4 years ago
- Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.☆24Aug 12, 2026Updated 2 months ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel.☆186Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆22Sep 30, 2026Updated last month
- ☆12Apr 29, 2025Updated last year
- a riscv32 rv32imc emulator written in c.☆33May 7, 2026Updated 5 months ago
- Stop-To-Ask-Questions-The-Stupid-Ways☆10Jan 12, 2022Updated 4 years ago
- ☆33Apr 10, 2026Updated 6 months ago
- Cross-platform IEC 60870-5-104 protocol simulator with Slave & Master — Rust + Tauri 2 + Vue 3☆45Updated this week
- The official NaplesPU hardware code repository☆37Jul 27, 2019Updated 7 years ago