RPTU-EIS / RISCV-CoreLinks
5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
☆13Updated 3 weeks ago
Alternatives and similar repositories for RISCV-Core
Users that are interested in RISCV-Core are comparing it to the libraries listed below
Sorting:
- DUTH RISC-V Superscalar Microprocessor☆33Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆21Updated 7 months ago
- The official NaplesPU hardware code repository☆20Updated 6 years ago
- RISC-V IOMMU in verilog☆20Updated 3 years ago
- ☆31Updated 5 years ago
- Open-source AMBA CHI infrastructures (supporting Issue B, E.b)☆31Updated this week
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆19Updated 9 months ago
- RISC-V 64 CPU☆10Updated 2 months ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆20Updated 8 months ago
- Pipelined 64-bit RISC-V core☆15Updated last year
- A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.☆30Updated 5 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year
- BlackParrot on Zynq☆47Updated last week
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆21Updated last week
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Updated last year
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆26Updated last month
- verification of simple axi-based cache☆18Updated 6 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 3 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆32Updated 2 years ago
- ☆16Updated last month
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆33Updated 5 years ago
- Direct Access Memory for MPSoC☆13Updated last week
- An almost empty chisel project as a starting point for hardware design☆33Updated 10 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆19Updated 8 months ago
- PCI Express controller model☆71Updated 3 years ago
- ☆33Updated last month
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Updated 2 weeks ago