5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
☆13Dec 4, 2025Updated 5 months ago
Alternatives and similar repositories for RISCV-Core
Users that are interested in RISCV-Core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆24Mar 2, 2023Updated 3 years ago
- A riscv emulator.☆19Feb 5, 2024Updated 2 years ago
- Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown …☆14Jan 17, 2025Updated last year
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 6 years ago
- 中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程☆30May 30, 2020Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- HITSZ 404 NOT FOUND NSCSCC22 project☆15Sep 8, 2022Updated 3 years ago
- SystemVerilog implemention of the TAGE branch predictor☆14May 26, 2021Updated 4 years ago
- risc-v 单周期和流水线cpu设计， 基于miniRV-1指令集，语言verilog☆11Feb 23, 2023Updated 3 years ago
- 5 Stage Pipelined RISC V Processor Design for RV32I Instruction Set☆10Sep 15, 2022Updated 3 years ago
- A small Neural Network Processor for Edge devices.☆19Nov 22, 2022Updated 3 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated last year
- simple 4-BIT CPU with 74-serials chip，origin by Kaoru Tonami in his book “How to build a CPU”☆14Oct 19, 2024Updated last year
- RISC-V IOMMU in verilog☆23Jun 18, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Jul 14, 2024Updated last year
- The official NaplesPU hardware code repository☆24Jul 27, 2019Updated 6 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Apr 12, 2020Updated 6 years ago
- A project for learning RISC-V architecture purpose☆27Nov 9, 2023Updated 2 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆23Nov 24, 2025Updated 5 months ago
- ☆26Sep 3, 2020Updated 5 years ago
- ☆67Aug 5, 2024Updated last year
- Pipelined 64-bit RISC-V core☆16Mar 7, 2024Updated 2 years ago
- This is a set of python codes that forecast electricity price in wholesale power markets using an integrated long-term recurrent convolut…☆15Oct 14, 2022Updated 3 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- ☆22Nov 25, 2023Updated 2 years ago
- [UAV] - [STM32F103] - 6 Axes sensor MPU6050 - Quaternion & Euler Angles Compute - PID Controller☆13Oct 17, 2016Updated 9 years ago
- Open-source Neural Processing Unit (NPU) from China ❤☆44Jan 29, 2025Updated last year
- Open Source Chip Project by University (OSCPU) - Zhoushan Core☆54Jul 23, 2022Updated 3 years ago
- RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.☆10Dec 11, 2020Updated 5 years ago
- Linux capable RISC-V SoC designed to be readable and useful.☆161Dec 19, 2025Updated 4 months ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated 2 months ago
- Ultra light weight small device firmware. Well architected to support MMU, SMP, low power idle. Can be run on various CPU architectures.☆20Aug 5, 2025Updated 9 months ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 11 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Microarchitecture diagrams of several CPUs☆49Apr 29, 2026Updated last week
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆24Jan 6, 2026Updated 4 months ago
- ☆31Apr 10, 2026Updated 3 weeks ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆18Aug 23, 2021Updated 4 years ago
- Scripts to automate building linux images for my emulator riscv_em☆16Oct 24, 2023Updated 2 years ago
- 基于小脚丫FPGA的电子琴，模拟钢琴音色，支持127个音符演奏，可通过转化MIDI文件实现自动播放☆16Aug 22, 2022Updated 3 years ago
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆36Oct 29, 2023Updated 2 years ago