zhemao / chisel-float
Floating point modules for CHISEL
☆31Updated 10 years ago
Alternatives and similar repositories for chisel-float:
Users that are interested in chisel-float are comparing it to the libraries listed below
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A Rocket-based RISC-V superscalar in-order core☆30Updated last week
- Tests for example Rocket Custom Coprocessors☆73Updated 5 years ago
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆39Updated this week
- For contributions of Chisel IP to the chisel community.☆59Updated 4 months ago
- Chisel components for FPGA projects☆121Updated last year
- CGRA framework with vectorization support.☆27Updated this week
- Next generation CGRA generator☆109Updated this week
- A GPU acceleration flow for RTL simulation with batch stimulus☆105Updated 11 months ago
- ☆15Updated 4 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆55Updated last month
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- high-performance RTL simulator☆153Updated 9 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated this week
- ☆55Updated this week
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆37Updated 6 months ago
- Chisel RISC-V Vector 1.0 Implementation☆87Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- A DSL for Systolic Arrays☆79Updated 6 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 10 months ago
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆39Updated last year
- Project repo for the POSH on-chip network generator☆44Updated this week
- Implementation of the Advanced Encryption Standard in Chisel☆20Updated 2 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆99Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆27Updated 5 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆88Updated 11 months ago
- A hardware synthesis framework with multi-level paradigm☆38Updated 2 months ago