Floating point modules for CHISEL
☆32Nov 2, 2014Updated 11 years ago
Alternatives and similar repositories for chisel-float
Users that are interested in chisel-float are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)☆11Dec 16, 2019Updated 6 years ago
- Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)☆25Feb 1, 2020Updated 6 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 12 years ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆54Apr 6, 2020Updated 6 years ago
- ☆13Feb 13, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Chisel Fixed-Point Arithmetic Library☆18Dec 15, 2025Updated 10 months ago
- Artifact repository for paper Automatic Generation of High-Performance Quantized Machine Learning Kernels☆17Oct 13, 2020Updated 6 years ago
- PyMTL3 wrapper of the Berkeley Hardfloat IP☆10Aug 9, 2023Updated 3 years ago
- ☆394Aug 19, 2026Updated 2 months ago
- Quasar 2.0: Chisel equivalent of SweRV-EL2☆35Apr 13, 2021Updated 5 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆251Apr 29, 2024Updated 2 years ago
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆225Jan 23, 2020Updated 6 years ago
- Chisel components for FPGA projects☆129Sep 19, 2023Updated 3 years ago
- Chisel Project for Integrating RTL code into SDAccel☆17Jan 12, 2018Updated 8 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- ☆12May 20, 2021Updated 5 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- Chisel module for performing Multi-Scalar Multiplication☆13Mar 25, 2022Updated 4 years ago
- educational microarchitectures for risc-v isa☆68Feb 18, 2019Updated 7 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- ☆20Feb 9, 2020Updated 6 years ago
- ☆27Sep 3, 2020Updated 6 years ago
- Layout, rendering ELK Graph generated by easysoc-firrtl, and display the graph as an interactive diagram to represent Chisel generated Fi…☆13Apr 1, 2022Updated 4 years ago
- Code for PyMTL Tutorial @ ISCA 2019☆11Jun 22, 2019Updated 7 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog design for hardware ray-caster game☆11Aug 14, 2023Updated 3 years ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 11 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆17Jul 17, 2016Updated 10 years ago
- VCML integration of Nvidia's NVDLA SystemC model☆14Apr 13, 2021Updated 5 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆66Jun 27, 2025Updated last year
- Examples for creating AXI-interfaced peripherals in Chisel☆76Nov 15, 2015Updated 10 years ago
- Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program☆32Sep 17, 2025Updated last year
- Lipsi: Probably the Smallest Processor in the World☆90Apr 15, 2024Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆110Jul 16, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元☆19Sep 16, 2022Updated 4 years ago
- Uart module written in chisel☆13Feb 19, 2016Updated 10 years ago
- A simple, easily extendable, RISCV assembler for the RV32I subset in Python.☆31Aug 18, 2023Updated 3 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Oct 5, 2017Updated 9 years ago
- A template project for beginning new Chisel work☆710Feb 24, 2026Updated 8 months ago
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆93Mar 26, 2023Updated 3 years ago
- GEMM and GEMM-Ops accelerator for PULP systems☆126Oct 22, 2026Updated last week