zhemao / chisel-float
Floating point modules for CHISEL
☆31Updated 10 years ago
Alternatives and similar repositories for chisel-float:
Users that are interested in chisel-float are comparing it to the libraries listed below
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 weeks ago
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- Tests for example Rocket Custom Coprocessors☆69Updated 5 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆71Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated 2 months ago
- ☆77Updated 2 years ago
- Chisel components for FPGA projects☆120Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆55Updated this week
- ☆15Updated 3 years ago
- A DSL for Systolic Arrays☆79Updated 6 years ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆85Updated 10 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆90Updated this week
- ☆54Updated this week
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆149Updated last year
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆37Updated last year
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated last week
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆99Updated last year
- Next generation CGRA generator☆109Updated this week
- CGRA framework with vectorization support.☆25Updated this week
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- ☆15Updated 2 years ago
- FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation☆91Updated last year
- A fault-injection framework using Chisel and FIRRTL☆34Updated 2 years ago
- ☆86Updated 11 months ago
- Template for projects using the Hwacha data-parallel accelerator☆34Updated 4 years ago