zhemao / chisel-float
Floating point modules for CHISEL
☆30Updated 10 years ago
Alternatives and similar repositories for chisel-float:
Users that are interested in chisel-float are comparing it to the libraries listed below
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆50Updated 4 years ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- Meta-Repository for Bespoke Silicon Group's Manycore Architecture (A.K.A HammerBlade)☆38Updated last month
- Tests for example Rocket Custom Coprocessors☆69Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆57Updated 2 months ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆54Updated last month
- A Rocket-based RISC-V superscalar in-order core☆29Updated 2 months ago
- A polyhedral compiler for hardware accelerators☆55Updated 5 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆98Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆99Updated 9 months ago
- ☆77Updated 2 years ago
- Chisel components for FPGA projects☆119Updated last year
- ☆15Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆40Updated 4 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆149Updated 11 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆48Updated last year
- Next generation CGRA generator☆108Updated this week
- (System)Verilog to Chisel translator☆109Updated 2 years ago
- CGRA framework with vectorization support.☆21Updated this week
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆20Updated this week
- high-performance RTL simulator☆149Updated 6 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆60Updated last year
- A Language for Closed-form High-level ARchitecture Modeling☆19Updated 4 years ago
- Project repo for the POSH on-chip network generator☆43Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆84Updated this week
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- Basic floating-point components for RISC-V processors☆63Updated 5 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- A DSL for Systolic Arrays☆78Updated 6 years ago