agile-hw / lecturesLinks
Lectures for the Agile Hardware Design course in Jupyter Notebooks
☆119Updated 3 months ago
Alternatives and similar repositories for lectures
Users that are interested in lectures are comparing it to the libraries listed below
Sorting:
- high-performance RTL simulator☆186Updated last year
- A dynamic verification library for Chisel.☆160Updated last year
- A Style Guide for the Chisel Hardware Construction Language☆109Updated 4 years ago
- Chisel Learning Journey☆111Updated 2 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- ☆82Updated last year
- A Chisel RTL generator for network-on-chip interconnects☆226Updated 3 months ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆195Updated last week
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆164Updated this week
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆98Updated last week
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Bluespec BSV HLHDL tutorial☆111Updated 9 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆136Updated last week
- Chisel RISC-V Vector 1.0 Implementation☆131Updated 4 months ago
- A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…☆57Updated last year
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆79Updated last month
- Advanced Architecture Labs with CVA6☆77Updated 2 years ago
- RISC-V Torture Test☆213Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- RISC-V Formal Verification Framework☆178Updated 3 weeks ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆117Updated last year
- An energy-efficient RISC-V floating-point compute cluster.☆123Updated 3 weeks ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆55Updated 6 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated last week
- An open-source UCIe implementation☆82Updated 2 weeks ago
- Open source high performance IEEE-754 floating unit☆89Updated last year
- Python wrapper for verilator model☆93Updated 2 years ago
- A Fast, Low-Overhead On-chip Network☆267Updated 2 weeks ago
- Provides dot visualizations of chisel/firrtl circuits☆123Updated 2 years ago
- Unit tests generator for RVV 1.0☆102Updated 3 months ago