agile-hw / lectures
Lectures for the Agile Hardware Design course in Jupyter Notebooks
☆85Updated 10 months ago
Alternatives and similar repositories for lectures:
Users that are interested in lectures are comparing it to the libraries listed below
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- A dynamic verification library for Chisel.☆145Updated 3 months ago
- A Chisel RTL generator for network-on-chip interconnects☆182Updated 2 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆64Updated 2 weeks ago
- high-performance RTL simulator☆151Updated 7 months ago
- (System)Verilog to Chisel translator☆111Updated 2 years ago
- ☆77Updated 11 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆99Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆89Updated this week
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆165Updated this week
- Advanced Architecture Labs with CVA6☆54Updated last year
- ☆77Updated 2 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆118Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆166Updated 6 months ago
- Chisel Learning Journey☆108Updated last year
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆50Updated 3 years ago
- Wrapper for Rocket-Chip on FPGAs☆129Updated 2 years ago
- ☆86Updated last year
- RISC-V Formal Verification Framework☆127Updated 3 weeks ago
- Pure digital components of a UCIe controller☆53Updated this week
- Unit tests generator for RVV 1.0☆74Updated last week
- A Rocket-based RISC-V superscalar in-order core☆29Updated last week
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆71Updated last year
- Vector processor for RISC-V vector ISA☆113Updated 4 years ago
- Bluespec BSV HLHDL tutorial☆98Updated 8 years ago
- Vector Acceleration IP core for RISC-V*☆166Updated this week
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆118Updated last week
- Verilog Configurable Cache☆169Updated 2 months ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆149Updated last year