agile-hw / lecturesLinks
Lectures for the Agile Hardware Design course in Jupyter Notebooks
☆104Updated 3 months ago
Alternatives and similar repositories for lectures
Users that are interested in lectures are comparing it to the libraries listed below
Sorting:
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A dynamic verification library for Chisel.☆154Updated 9 months ago
- high-performance RTL simulator☆173Updated last year
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆89Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆207Updated this week
- Chisel RISC-V Vector 1.0 Implementation☆108Updated 3 months ago
- Chisel Learning Journey☆109Updated 2 years ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆174Updated last month
- A Fast, Low-Overhead On-chip Network☆221Updated 3 weeks ago
- Vector Acceleration IP core for RISC-V*☆182Updated 3 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆76Updated 9 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆99Updated 2 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆179Updated 3 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- ☆81Updated last year
- Unit tests generator for RVV 1.0☆89Updated last week
- Provides dot visualizations of chisel/firrtl circuits☆121Updated 2 years ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆114Updated this week
- Open source high performance IEEE-754 floating unit☆83Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last week
- ☆97Updated last year
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆207Updated 2 weeks ago
- RISC-V Formal Verification Framework☆145Updated this week
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆125Updated last week
- For contributions of Chisel IP to the chisel community.☆65Updated 9 months ago
- Advanced Architecture Labs with CVA6☆65Updated last year
- Bluespec BSV HLHDL tutorial☆108Updated 9 years ago
- Pure digital components of a UCIe controller☆67Updated last month