agile-hw / lecturesLinks
Lectures for the Agile Hardware Design course in Jupyter Notebooks
☆118Updated 2 months ago
Alternatives and similar repositories for lectures
Users that are interested in lectures are comparing it to the libraries listed below
Sorting:
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A dynamic verification library for Chisel.☆159Updated last year
- high-performance RTL simulator☆185Updated last year
- Chisel Learning Journey☆111Updated 2 years ago
- (System)Verilog to Chisel translator☆116Updated 3 years ago
- ☆82Updated last year
- Bluespec BSV HLHDL tutorial☆111Updated 9 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆95Updated last month
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆135Updated this week
- A Chisel RTL generator for network-on-chip interconnects☆224Updated 2 months ago
- Examples for creating AXI-interfaced peripherals in Chisel☆75Updated 10 years ago
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆193Updated 4 months ago
- Tests for example Rocket Custom Coprocessors☆75Updated 5 years ago
- Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.☆19Updated 3 weeks ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆182Updated 8 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆122Updated last week
- A Fast, Low-Overhead On-chip Network☆264Updated this week
- A teaching-focused RISC-V CPU design used at UC Davis☆153Updated 2 years ago
- Microarchitecture implementation of the decoupled vector-fetch accelerator☆163Updated 2 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆62Updated 4 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆78Updated last month
- Wrapper for Rocket-Chip on FPGAs☆138Updated 3 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆170Updated 5 years ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆160Updated this week
- Advanced Architecture Labs with CVA6☆73Updated 2 years ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆152Updated last week
- Chisel RISC-V Vector 1.0 Implementation☆128Updated 3 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago
- Open-source high-performance non-blocking cache☆92Updated last month
- RISC-V Torture Test☆211Updated last year