Alternatives and similar repositories for RISCV-FiveStage:

Users that are interested in RISCV-FiveStage are comparing it to the libraries listed below

• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆172Updated 8 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆79Updated 5 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆149Updated this week
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆155Updated 2 weeks ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last month
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆118Updated last year
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆102Updated 9 months ago
• leros-dev / leros
  A Tiny Processor Core
  ☆107Updated 2 weeks ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆83Updated last week
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆112Updated 2 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆83Updated 11 months ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆223Updated 4 months ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆157Updated 2 months ago
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆204Updated 7 months ago
• SpinalHDL / NaxRiscv
  ☆279Updated 2 weeks ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆129Updated 2 months ago
• antmicro / fastvdma
  Antmicro's fast, vendor-neutral DMA IP in Chisel
  ☆114Updated 4 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆248Updated last month
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆110Updated 6 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆108Updated last year
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆148Updated 8 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆225Updated 4 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆247Updated 4 months ago
• ucb-bar / dsptools
  A Library of Chisel3 Tools for Digital Signal Processing
  ☆234Updated 11 months ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆100Updated 5 years ago
• chipsalliance / VeeR-ISS
  ☆131Updated last year
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆89Updated this week
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆248Updated 2 years ago
• freechipsproject / ip-contributions
  For contributions of Chisel IP to the chisel community.
  ☆60Updated 4 months ago