Alternatives and similar repositories for MIPSCPU

Users that are interested in MIPSCPU are comparing it to the libraries listed below

• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆13Updated last year
• LainChip / LainCore
  Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.
  ☆45Updated last year
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆37Updated 4 years ago
• Jeremy2001-chen / OS-RISCV
  A small RISC-V kernel coding by C, tested on sifive unmatched board.
  ☆16Updated 3 years ago
• thu-cs-lab / verilog-coding-standard
  Recommended coding standard of Verilog and SystemVerilog.
  ☆36Updated 4 years ago
• AlwenXXD / nscscc2021
  龙芯杯21个人赛作品
  ☆36Updated 4 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆61Updated 3 years ago
• jiegec / cpu
  Microarchitecture diagrams of several CPUs
  ☆46Updated 3 weeks ago
• thu-cs-lab / thinpad_top
  Project template for Artix-7 based Thinpad board
  ☆52Updated 4 months ago
• howardlau1999 / yatcpu
  Yet another toy CPU.
  ☆92Updated 2 years ago
• pku-liang / Hestia
  ☆17Updated 10 months ago
• jiegec / naiverouter
  A router IP written in Verilog.
  ☆12Updated 6 years ago
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆51Updated last month
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆50Updated 2 years ago
• z4yx / supervisor-mips32
  计算机组成原理课程32位监控程序
  ☆50Updated 5 years ago
• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆10Updated 3 years ago
• comparch-security / FlexiCAS
  A Flexible Cache Architectural Simulator
  ☆16Updated 4 months ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆40Updated 2 years ago
• gmlayer0 / wired
  Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.
  ☆32Updated last year
• cyyself / cemu
  A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …
  ☆119Updated last year
• Seeker0472 / ysyx-linux
  给NEMU移植Linux Kernel!
  ☆22Updated 8 months ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 3 years ago
• jiegec / kb
  My knowledge base
  ☆77Updated last week
• NOP-Processor / NOP-Core
  High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)
  ☆82Updated 2 years ago
• jiegec / cpu-micro-benchmarks
  CPU micro benchmarks
  ☆76Updated 2 weeks ago
• OSCPU / archbench
  ☆11Updated last month
• pku-liang / ksim
  ☆52Updated last year