Alternatives and similar repositories for verilog_library:

Users that are interested in verilog_library are comparing it to the libraries listed below

• OpenXiangShan / XS-Verilog-Library
  ☆39Updated 2 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆57Updated last year
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆52Updated 10 years ago
• pulp-platform / axi_spi_master
  ☆20Updated 5 years ago
• yaozhaosh / e200_opensource
  The Ultra-Low Power RISC Core
  ☆15Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆88Updated 4 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆93Updated 4 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆45Updated 4 years ago
• ForrestBlue / cortexm0ds
  ☆57Updated 8 years ago
• wanderingnail / AXI_DMA
  ☆16Updated 2 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆35Updated 9 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆72Updated 6 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆30Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆103Updated 10 years ago
• RV-BOSC / OpenNoC
  ☆76Updated this week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆88Updated last year
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆39Updated 4 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆93Updated 3 years ago
• light-ly / chisel-template
  自建 chisel 工程模板
  ☆12Updated last year
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆83Updated 8 months ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆36Updated 2 years ago
• kuladeepsaireddy / OpenNoc
  ☆26Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 8 months ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆130Updated last month
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆27Updated 2 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆46Updated 5 years ago
• sunyata000 / PODES-M0O
  A VerilogHDL MCU Core based ARMv6 Cortex-M0
  ☆21Updated 4 years ago
• lizhirui / DreamCore
  ☆63Updated 2 years ago
• panweitao / riscvv
  an open source uvm verification platform for e200 (riscv)
  ☆26Updated 6 years ago