OpenXiangShan / nexus-am
☆31Updated this week
Related projects ⓘ
Alternatives and complementary repositories for nexus-am
- Open source high performance IEEE-754 floating unit☆60Updated 8 months ago
- Open-source non-blocking L2 cache☆33Updated this week
- Open-source high-performance non-blocking cache☆67Updated last month
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆90Updated this week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆27Updated 6 months ago
- ☆74Updated 2 years ago
- The multi-core cluster of a PULP system.☆56Updated last week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆21Updated 8 months ago
- ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆25Updated this week
- Wrappers for open source FPU hardware implementations.☆31Updated 7 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆52Updated last year
- ☆56Updated 3 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 3 months ago
- Simple runtime for Pulp platforms☆34Updated last week
- ☆32Updated last week
- ☆80Updated 3 weeks ago
- 64-bit multicore Linux-capable RISC-V processor☆78Updated 2 months ago
- Provides various testers for chisel users☆99Updated last year
- A RISC-V Core (RV32I) written in Chisel HDL☆97Updated 5 months ago
- ☆31Updated last month
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Updated last year
- For contributions of Chisel IP to the chisel community.☆55Updated this week
- ☆39Updated 2 years ago
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆13Updated 7 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- AIA IP compliant with the RISC-V AIA spec☆30Updated 2 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆32Updated 3 weeks ago
- ☆81Updated 2 years ago
- ☆40Updated 5 months ago