OpenXiangShan / nexus-amLinks
☆35Updated last week
Alternatives and similar repositories for nexus-am
Users that are interested in nexus-am are comparing it to the libraries listed below
Sorting:
- Open-source high-performance non-blocking cache☆82Updated last week
- Open-source non-blocking L2 cache☆43Updated this week
- Open source high performance IEEE-754 floating unit☆72Updated last year
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated last year
- This repo includes XiangShan's function units☆26Updated this week
- chipyard in mill :P☆78Updated last year
- RISC-V Vector (RVV) Automatic Tests Generator with full instructions coverage, including self-checking test and signature test (RISC-V Co…☆15Updated last year
- XiangShan Frontend Develop Environment☆58Updated 2 weeks ago
- Chisel RISC-V Vector 1.0 Implementation☆98Updated last month
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- ☆42Updated 3 years ago
- For contributions of Chisel IP to the chisel community.☆61Updated 7 months ago
- ☆86Updated 3 years ago
- Rewrite XuanTieC910 with chisel3☆12Updated 2 years ago
- Home of the specification to connect SemiDynamic's RISC-V cores to your own RISC-V Vector Unit☆37Updated 3 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆32Updated last year
- ☆35Updated 10 months ago
- RISC-V architecture concurrency model litmus tests☆78Updated last week
- ☆67Updated 4 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆105Updated last year
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆94Updated 2 months ago
- ☆33Updated 2 months ago
- AIA IP compliant with the RISC-V AIA spec☆41Updated 4 months ago
- ☆31Updated 2 months ago
- RISC-V Packed SIMD Extension☆147Updated last year
- upstream: https://github.com/RALC88/gem5☆31Updated 2 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- Setup scripts and files needed to compile CoreMark on RISC-V☆68Updated 10 months ago
- A bare-metal application to test specific features of the risc-v hypervisor extension☆40Updated last year
- A RISC-V Core (RV32I) written in Chisel HDL☆102Updated 2 months ago