OpenXiangShan / nexus-amLinks
☆35Updated this week
Alternatives and similar repositories for nexus-am
Users that are interested in nexus-am are comparing it to the libraries listed below
Sorting:
- Open-source high-performance non-blocking cache☆86Updated last month
- Open-source non-blocking L2 cache☆44Updated this week
- Open source high performance IEEE-754 floating unit☆80Updated last year
- This repo includes XiangShan's function units☆26Updated this week
- RISC-V Core Local Interrupt Controller (CLINT)☆27Updated 3 weeks ago
- ☆47Updated 2 months ago
- The specification for the FIRRTL language☆58Updated this week
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆40Updated last year
- For contributions of Chisel IP to the chisel community.☆64Updated 8 months ago
- chipyard in mill :P☆78Updated last year
- ☆35Updated last year
- pulp_soc is the core building component of PULP based SoCs☆80Updated 4 months ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆37Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆93Updated 2 months ago
- ☆86Updated 3 years ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- ☆25Updated 4 months ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- Wrappers for open source FPU hardware implementations.☆32Updated last year
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 3 months ago
- Chisel RISC-V Vector 1.0 Implementation☆103Updated 2 months ago
- ☆42Updated 3 years ago
- Simple runtime for Pulp platforms☆48Updated this week
- Vortex Graphics☆80Updated 9 months ago
- XiangShan Frontend Develop Environment☆60Updated this week
- ☆84Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆65Updated 2 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Updated last year