cnrv / riscv-soc-bookLinks
关于RISC-V你所需要知道的一切
☆559Updated 2 years ago
Alternatives and similar repositories for riscv-soc-book
Users that are interested in riscv-soc-book are comparing it to the libraries listed below
Sorting:
- 为推广RISC-V尽些薄力☆312Updated 2 years ago
- Documentation for XiangShan☆425Updated this week
- A translation project of the RISC-V reader☆174Updated last year
- ☆124Updated 3 years ago
- 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料☆233Updated 4 years ago
- Super fast RISC-V ISA emulator for XiangShan processor☆299Updated last week
- NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.☆603Updated 5 years ago
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆177Updated 4 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆598Updated last year
- 一生一芯的信息发布和 内容网站☆135Updated last year
- riscv资料、论文等☆144Updated 7 years ago
- Riscv32 CPU Project☆94Updated 7 years ago
- ☆210Updated 7 months ago
- GPGPU processor supporting RISCV-V extension, developed with Chisel HDL☆824Updated this week
- An exquisite superscalar RV32GC processor.☆161Updated 10 months ago
- RISC-V SoC designed by students in UCAS☆1,487Updated this week
- Generator Bootcamp Material: Learn Chisel the Right Way☆1,080Updated last year
- NJU Virtual Board☆294Updated 2 months ago
- ☆221Updated 2 years ago
- Digital Design with Chisel☆870Updated last week
- Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro☆1,002Updated 3 months ago
- ☆157Updated 2 weeks ago
- A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation☆197Updated last year
- The Ultra-Low Power RISC-V Core☆1,644Updated 3 months ago
- The Ultra-Low Power RISC Core☆49Updated 6 years ago
- A very simple and easy to understand RISC-V core.☆1,325Updated 2 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆187Updated last year
- chisel tutorial exercises and answers☆734Updated 3 years ago
- 一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。☆593Updated 2 years ago
- ☆167Updated 4 years ago