Alternatives and similar repositories for riscv-soc-book

Users that are interested in riscv-soc-book are comparing it to the libraries listed below

• cnrv / home
  为推广RISC-V尽些薄力
  ☆312Updated 2 years ago
• OpenXiangShan / XiangShan-doc
  Documentation for XiangShan
  ☆427Updated this week
• OSCPU / NutShell-doc
  ☆124Updated 3 years ago
• Lingrui98 / RISC-V-book
  A translation project of the RISC-V reader
  ☆174Updated last year
• plctlab / writing-your-first-riscv-simulator
  《从零开始的RISC-V模拟器开发》配套的PPT和教学资料
  ☆234Updated 4 years ago
• OpenXiangShan / NEMU
  Super fast RISC-V ISA emulator for XiangShan processor
  ☆300Updated this week
• MaxXSoft / Fuxi
  Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
  ☆180Updated 4 years ago
• trivialmips / nontrivial-mips
  NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
  ☆604Updated 5 years ago
• OSCPU / ysyx
  一生一芯的信息发布和内容网站
  ☆135Updated 2 years ago
• LiHao217 / RISC-V_article_paper_src
  riscv资料、论文等
  ☆144Updated 7 years ago
• lmxyy / Computer-Architecture-Task-2
  Riscv32 CPU Project
  ☆94Updated 7 years ago
• NJU-ProjectN / nvboard
  NJU Virtual Board
  ☆295Updated 3 months ago
• THU-DSP-LAB / ventus-gpgpu
  GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
  ☆845Updated last week
• ucb-bar / riscv-mini
  Simple RISC-V 3-stage Pipeline in Chisel
  ☆601Updated last year
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆188Updated last year
• runninglinuxkernel / riscv_programming_practice
  ☆222Updated 2 years ago
• hehao98 / RISCV-Simulator
  A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation
  ☆200Updated last year
• whik / e200_opensource
  The Ultra-Low Power RISC Core
  ☆49Updated 6 years ago
• OSCPU / ysyx-workbench
  ☆158Updated last week
• DawnCarol / DawnCarol
  ☆210Updated 7 months ago
• OSCPU / NutShell
  RISC-V SoC designed by students in UCAS
  ☆1,489Updated 3 weeks ago
• freechipsproject / chisel-bootcamp
  Generator Bootcamp Material: Learn Chisel the Right Way
  ☆1,087Updated last year
• rv2036 / rv2036-website
  Official website for Jiachen Project (甲辰计划).
  ☆61Updated last month
• liangkangnan / tinyriscv
  A very simple and easy to understand RISC-V core.
  ☆1,334Updated 2 years ago
• LoveLonelyTime / Bergamot
  An exquisite superscalar RV32GC processor.
  ☆162Updated 10 months ago
• LvNA-system / labeled-RISC-V
  ☆168Updated 4 years ago
• riscv-non-isa / riscv-elf-psabi-doc
  A RISC-V ELF psABI Document
  ☆816Updated last week
• schoeberl / chisel-book
  Digital Design with Chisel
  ☆879Updated 2 weeks ago
• riscv-mcu / e203_hbirdv2
  The Ultra-Low Power RISC-V Core
  ☆1,664Updated 4 months ago
• zach0zhang / Single_instruction_cycle_OpenMIPS
  通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器
  ☆206Updated 3 years ago