Alternatives and similar repositories for UnityChipForXiangShan

Users that are interested in UnityChipForXiangShan are comparing it to the libraries listed below

• XS-MLVP / picker
  Pick your favorite language to verify your chip.
  ☆74Updated this week
• XS-MLVP / toffee
  A framework for building hardware verification platform using software method
  ☆30Updated 3 weeks ago
• OpenXiangShan / XiangShan-Design-Doc
  Documentation for XiangShan Design
  ☆37Updated 2 months ago
• OSCPU / ysyxSoC
  ☆91Updated 2 months ago
• OSCPU-Zhoushan / Zhoushan
  Open Source Chip Project by University (OSCPU) - Zhoushan Core
  ☆54Updated 3 years ago
• OSCPU / chisel-playground
  ☆68Updated 10 months ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆165Updated this week
• XS-MLVP / Example-NutShellCache
  开放验证平台NutShell Cache验证案例
  ☆11Updated 3 weeks ago
• OSCPU / yosys-sta
  ☆87Updated last month
• lizhirui / DreamCoreV2
  ☆22Updated 2 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆30Updated this week
• tastynoob / aura-core
  "aura" my super-scalar O3 cpu core
  ☆24Updated last year
• Jpz-sdju / trinity
  ☆32Updated 4 months ago
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 3 weeks ago
• OpenXiangShan / GEM5
  ☆117Updated this week
• cyyself / soc-simulator
  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.
  ☆50Updated 2 months ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆69Updated last year
• FurryAcetylCoA / gtkwave-filter-process-RISC
  A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave
  ☆31Updated 8 months ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆38Updated last year
• CherrySprings / CherrySprings
  ☆19Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆71Updated last year
• sequencer / arithmetic
  ☆33Updated 9 months ago
• pulp-platform / fpu
  ☆57Updated 6 years ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆86Updated last year
• ysyx-ta / ysyx-summer-readings
  ☆67Updated last year
• OpenXiangShan / XSAI
  A fork of Xiangshan for AI
  ☆35Updated this week
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆78Updated 5 years ago
• f0rm2l1n / riscv-simulator-guide
  RISC-V模拟器，相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册
  ☆53Updated 5 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆44Updated 2 years ago