Crowdsourced Verification Project (UnityChip Verification) for the Xiangshan Processor
☆48Apr 3, 2026Updated last week
Alternatives and similar repositories for UnityChipForXiangShan
Users that are interested in UnityChipForXiangShan are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A framework for building hardware verification platform using software method☆35Dec 24, 2025Updated 3 months ago
- Pick your favorite language to verify your chip.☆83Updated this week
- 香山微架构开放验证第一期：昆明湖BPU模块UT测试模块及环境☆30Oct 20, 2024Updated last year
- Documentation for XiangShan Design☆48Mar 31, 2026Updated last week
- ☆13Apr 3, 2026Updated last week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- UVM components for DSP tasks (MODulation/DEModulation)☆15Mar 2, 2022Updated 4 years ago
- Open-Source EDA workshop for RISC-V community☆12Jul 27, 2022Updated 3 years ago
- UCAS SEP扩展脚本 - 课程评估辅助 etc.☆12Apr 3, 2025Updated last year
- UnityChip Verification AI-Agent☆130Updated this week
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Mar 30, 2026Updated last week
- Spike, a RISC-V ISA Simulator☆10Jan 22, 2026Updated 2 months ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- ☆17Mar 13, 2026Updated 3 weeks ago
- ☆10Dec 17, 2025Updated 3 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆31Mar 29, 2026Updated 2 weeks ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆36Dec 24, 2024Updated last year
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Feb 23, 2026Updated last month
- Documentation for XiangShan☆434Apr 2, 2026Updated last week
- ☆227Jun 25, 2025Updated 9 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆70Updated this week
- SystemVerilog Functional Coverage for RISC-V ISA☆34Dec 11, 2025Updated 4 months ago
- CV32E40X Design-Verification environment☆16Mar 25, 2024Updated 2 years ago
- Implementation of a binary search tree algorithm in a FPGA/ASIC IP☆21Sep 5, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.☆16Sep 27, 2022Updated 3 years ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆16Feb 12, 2026Updated 2 months ago
- A dynamic verification library for Chisel.☆160Nov 9, 2024Updated last year
- ☆43Mar 31, 2025Updated last year
- A fork of Xiangshan for AI☆39Mar 30, 2026Updated last week
- This repo stores a more profound view of Computer Architecture: A Quantitative Approach that tells multi-tenancy, virtualize, fine graine…☆29Dec 24, 2025Updated 3 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Jul 5, 2025Updated 9 months ago
- RISC-V muticycle implementation in VHDL. Core supports multiple peripherals and interruptions using a simple local interrupt controller.☆22Dec 19, 2025Updated 3 months ago
- RISC-V Development Boards Wandering Project. It is part of the Jiachen Project.☆46Feb 4, 2026Updated 2 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Integer Multiplier Generator for Verilog☆24Jul 4, 2025Updated 9 months ago
- Open-source AI acceleration on FPGA: from ONNX to RTL☆53Mar 24, 2026Updated 2 weeks ago
- Contains examples to start with Kactus2.☆23Aug 5, 2024Updated last year
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- ☆14Oct 11, 2024Updated last year
- ☆17Mar 26, 2025Updated last year
- ☆22Nov 25, 2023Updated 2 years ago