Alternatives and similar repositories for ixayoi

Users that are interested in ixayoi are comparing it to the libraries listed below

• jiegec / verilog-lang
  A hand-written recursive decent Verilog parser.
  ☆11Updated 2 years ago
• CircuitCoder / MeoWave
  ☆10Updated last year
• dramforever / finlog
  Compiling finite generators to digital logic. WIP
  ☆14Updated 4 years ago
• CircuitCoder / ChannelOS
  What if everything is a io_uring?
  ☆16Updated 2 years ago
• jiegec / rvv-kernels
  Implements kernels with RISC-V Vector
  ☆22Updated 2 years ago
• z4yx / vivado-docker
  Dockerfile with Vivado for CI
  ☆28Updated 5 years ago
• jiegec / chisel-memory-lower
  Lower chisel memories to SRAM macros
  ☆12Updated last year
• CircuitCoder / mill
  RV32I by cats
  ☆16Updated last year
• chipsalliance / rocket-chip-fpga-shells
  Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards
  ☆18Updated 6 months ago
• rcore-os / x86-smpboot
  Booting multi-processors on x86 bare-metal.
  ☆11Updated 3 years ago
• CircuitCoder / ld.meow.so
  Toy ELF dynlinker & interp
  ☆10Updated last year
• jiegec / verilog-format
  A naive verilog/systemverilog formatter
  ☆21Updated 2 months ago
• monkey2000 / LPi4A-Case
  A 3d printed case design for Lichee Pi 4A
  ☆12Updated 2 years ago
• losfair / Violet
  Superscalar RISC-V processor written in Clash.
  ☆34Updated 2 years ago
• dramforever / urvirt
  User-mode trap-and-emulate hypervisor for RISC-V
  ☆13Updated 3 years ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆31Updated last year
• KireinaHoro / khtcp
  PKU CompNet'19 Lab 2 - Homebrew TCP
  ☆12Updated 5 years ago
• CircuitCoder / cidr-calc
  CIDR union / subtraction
  ☆14Updated 4 months ago
• cyyself / cyyrv64
  My RV64 CPU (Work in progress)
  ☆19Updated 2 years ago
• riscv / riscv-control-transfer-records
  This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…
  ☆21Updated 3 months ago
• char-fish-after-lunch / SystemOnCat
  An SoC with multiple RISC-V IMA processors.
  ☆19Updated 6 years ago
• KireinaHoro / khemu
  Binary translation in Rust
  ☆13Updated 4 years ago
• rustsbi / serde-device-tree
  Serialize & deserialize device tree binary using serde
  ☆20Updated last month
• wangrunji0408 / rjrouter
  [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)
  ☆14Updated 4 years ago
• thu-cs-lab / JieLabs-Web
  Backend & Frontend for JieLabs
  ☆22Updated 2 years ago
• jiegec / apple-pmu
  Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS
  ☆14Updated 2 months ago
• circt / arc-tests
  A collection of tests and benchmarks for the Arc simulation backend of CIRCT
  ☆28Updated 3 months ago
• CircuitCoder / MeowThink
  A mini (consistent-wannabe) proof-assistant with power roughly equivalent to intelligence of a two month old cat
  ☆17Updated 3 years ago
• sequencer / zaozi
  A eDSL framework based on Scala and MLIR, focusing on the Hardware design.
  ☆36Updated this week
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆62Updated 3 years ago