dramforever / ixayoiLinks
(WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
☆12Updated 4 years ago
Alternatives and similar repositories for ixayoi
Users that are interested in ixayoi are comparing it to the libraries listed below
Sorting:
- A hand-written recursive decent Verilog parser.☆10Updated 3 years ago
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Dockerfile with Vivado for CI☆27Updated 5 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Compiling finite generators to digital logic. WIP☆13Updated 5 years ago
- What if everything is a io_uring?☆16Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆41Updated last month
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- Wrappers for open source FPU hardware implementations.☆34Updated last year
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- Run Rocket Chip on VCU128☆30Updated 10 months ago
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆19Updated 10 months ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 7 years ago
- RV32I by cats☆15Updated 2 years ago
- A naive verilog/systemverilog formatter☆21Updated 6 months ago
- Lower chisel memories to SRAM macros☆12Updated last year
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆30Updated last month
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- Remote JTAG server for remote debugging☆41Updated last year
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- A 3d printed case design for Lichee Pi 4A☆12Updated 2 years ago
- Open-Source EDA workshop for RISC-V community☆12Updated 3 years ago
- Dump Apple PMU counter definitions from `/usr/share/kpep` in macOS☆16Updated 2 weeks ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Updated 3 years ago
- Microarchitecture diagrams of several CPUs☆43Updated 3 weeks ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆12Updated 4 years ago
- My knowledge base☆67Updated 2 weeks ago
- chipyard in mill :P☆78Updated last year
- The 'missing header' for Chisel☆21Updated 6 months ago