dramforever / ixayoiLinks
(WIP) A relatively simple pipelined RISC-V core, written in Bluespec SystemVerilog
☆12Updated 3 years ago
Alternatives and similar repositories for ixayoi
Users that are interested in ixayoi are comparing it to the libraries listed below
Sorting:
- A hand-written recursive decent Verilog parser.☆11Updated 2 years ago
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- Dockerfile with Vivado for CI☆28Updated 5 years ago
- RV32I by cats☆16Updated last year
- My RV64 CPU (Work in progress)☆19Updated 2 years ago
- Compiling finite generators to digital logic. WIP☆14Updated 4 years ago
- What if everything is a io_uring?☆16Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆62Updated 3 years ago
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- Wrappers for open source FPU hardware implementations.☆33Updated last year
- Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards☆19Updated 8 months ago
- User-mode trap-and-emulate hypervisor for RISC-V☆13Updated 3 years ago
- Run Rocket Chip on VCU128☆30Updated 8 months ago
- An SoC with multiple RISC-V IMA processors.☆19Updated 7 years ago
- WIP: A fork of OpenSBI, with software-emulated hypervisor extension support☆40Updated 5 months ago
- A collection of tests and benchmarks for the Arc simulation backend of CIRCT☆30Updated 5 months ago
- This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usag…☆23Updated 5 months ago
- Open-Source EDA workshop for RISC-V community☆12Updated 3 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆19Updated 2 years ago
- Lower chisel memories to SRAM macros☆12Updated last year
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- A 3d printed case design for Lichee Pi 4A☆12Updated 2 years ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆12Updated 4 years ago
- Microarchitecture diagrams of several CPUs☆37Updated 3 weeks ago
- Formal verification tools for Chisel and RISC-V☆13Updated last year
- The MIPS CPU from previous CQU NSCSCC team and debugged by me running uCore MIPS porting successfully☆9Updated 4 years ago
- Remote JTAG server for remote debugging☆40Updated last year
- A naive verilog/systemverilog formatter☆21Updated 4 months ago
- A eDSL framework based on Scala and MLIR, focusing on the Hardware design.☆48Updated last week
- A Hardware Pipeline Description Language☆45Updated 3 weeks ago