NVlabs / INSTALinks
☆85Updated 2 months ago
Alternatives and similar repositories for INSTA
Users that are interested in INSTA are comparing it to the libraries listed below
Sorting:
- Collection of digital hardware modules & projects (benchmarks)☆59Updated last month
- ☆74Updated 2 months ago
- ☆45Updated last year
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆84Updated 3 months ago
- ☆181Updated 5 months ago
- GPU-based logic synthesis tool☆90Updated 2 weeks ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆105Updated last year
- This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024☆51Updated 7 months ago
- The first version of TritonPart☆28Updated last year
- Official implementation of paper "Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation".☆47Updated 2 months ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆51Updated 3 months ago
- ☆39Updated 2 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆55Updated 7 months ago
- ☆23Updated 9 months ago
- reference block design for the ASAP7nm library in Cadence Innovus☆50Updated last year
- ☆34Updated 2 years ago
- ☆44Updated 11 months ago
- DATC RDF☆50Updated 5 years ago
- ☆53Updated 2 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆182Updated 5 years ago
- ☆24Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆135Updated 2 months ago
- ☆82Updated this week
- IDEA project source files☆108Updated 2 weeks ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆151Updated 4 months ago
- ☆31Updated 3 years ago
- Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".☆50Updated 2 months ago
- ☆22Updated last year
- A Standalone Structural Verilog Parser☆97Updated 3 years ago