Alternatives and similar repositories for yosys-slang

Users that are interested in yosys-slang are comparing it to the libraries listed below

• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆226Updated 10 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated 2 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆215Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆167Updated 2 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆245Updated 4 months ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆163Updated 2 months ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆178Updated 5 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆73Updated 4 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• chipsalliance / uvm-verilator
  ☆113Updated 2 months ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆137Updated 2 weeks ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆52Updated 9 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 3 months ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆122Updated 4 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• mciepluc / cocotb-coverage
  Functional Coverage and Constrained Randomization Extensions for Cocotb
  ☆119Updated 4 months ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆64Updated 4 years ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆74Updated last month
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 6 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆82Updated last week
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• openecos-projects / icsprout55-pdk
  55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.
  ☆166Updated last month
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆113Updated this week
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆28Updated 4 years ago
• antmicro / sv-bugpoint
  ☆35Updated last week