povik / yosys-slangLinks
SystemVerilog frontend for Yosys
☆184Updated this week
Alternatives and similar repositories for yosys-slang
Users that are interested in yosys-slang are comparing it to the libraries listed below
Sorting:
- SystemVerilog synthesis tool☆220Updated 9 months ago
- WAL enables programmable waveform analysis.☆163Updated last month
- A complete open-source design-for-testing (DFT) Solution☆173Updated 3 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- A SystemVerilog source file pickler.☆60Updated last year
- Fabric generator and CAD tools.☆214Updated this week
- An automatic clock gating utility☆51Updated 8 months ago
- Control and status register code generator toolchain☆162Updated 3 weeks ago
- Python packages providing a library for Verification Stimulus and Coverage☆134Updated last month
- ☆33Updated 11 months ago
- A command-line tool for displaying vcd waveforms.☆65Updated last year
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 10 months ago
- RISC-V Nox core☆71Updated 5 months ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆175Updated last week
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆119Updated 2 months ago
- A Standalone Structural Verilog Parser☆99Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- ☆110Updated last month
- Making cocotb testbenches that bit easier☆36Updated last month
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆96Updated last year
- ☆97Updated this week
- 55nm CMOS Open Source PDK by ICsprout Integrated Circuit Co., Ltd.☆143Updated last week
- Mutation Cover with Yosys (MCY)☆89Updated 3 weeks ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- ☆88Updated 2 months ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆102Updated 3 years ago
- Experimental flows using nextpnr for Xilinx devices☆250Updated last year